Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12111684 | Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module | Douglas J. Malone, Andreas H. A. Arp, Franklin M. Baez, Daniel M. Dreps, Jason L. Frankel +2 more | 2024-10-08 |
| 11775004 | Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module | Douglas J. Malone, Andreas H. A. Arp, Franklin M. Baez, Daniel M. Dreps, Jason L. Frankel +2 more | 2023-10-03 |
| 11714449 | High-speed deserializer with programmable and timing robust data slip function | Ze Zhang, Dereje G. Yilma, Glen A. Wiedemeier | 2023-08-01 |
| 11662381 | Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers | Nathan Ross Blanchard, Venkat Harish Nammi, Dereje G. Yilma, Glen A. Wiedemeier, Jeffrey Kwabena Okyere +4 more | 2023-05-30 |
| 11632103 | High-speed voltage clamp for unterminated transmission lines | Glen A. Wiedemeier, Daniel M. Dreps | 2023-04-18 |
| 11606082 | Adjustable phase shifter | Yang You, Glen A. Wiedemeier, Tyler Bohlke, Daniel M. Dreps | 2023-03-14 |
| 11558045 | Phase rotator | Yang You, Venkat Harish Nammi, Pier Andrea Francese, Glen A. Wiedemeier, Daniel M. Dreps | 2023-01-17 |
| 11528102 | Built-in-self-test and characterization of a high speed serial link receiver | Dereje G. Yilma, Nathan Ross Blanchard, Erik English, Glen A. Wiedemeier, Jeffrey Kwabena Okyere +5 more | 2022-12-13 |
| 11201767 | Continuous time linear equalization including a low frequency equalization circuit which maintains DC gain | Erik English, Pier Andrea Francese | 2021-12-14 |
| 11049830 | Level shifting between interconnected chips having different voltage potentials | Daniel M. Dreps | 2021-06-29 |
| 10958248 | Jitter attenuation buffer structure | Yang You, Glen A. Wiedemeier, Jeffrey Kwabena Okyere, Daniel M. Dreps, Sudipto Chakraborty | 2021-03-23 |
| 10931269 | Early mode protection for chip-to-chip synchronous interfaces | Michael A. Sperling, Pawel Owczarczyk, Douglas J. Malone | 2021-02-23 |
| 10826810 | Versatile signal detector circuit using common mode shift with all-pass characteristics | Yang You, Pier Andrea Francese, Glen A. Wiedemeier, Daniel M. Dreps | 2020-11-03 |
| 9659121 | Deterministic and statistical timing modeling for differential circuits | Hemlata Gupta, Jin Hu, Vasant Rao, Debjit Sinha | 2017-05-23 |