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USPTO Patent Rankings Data through Dec 31, 2025
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Debjit Sinha — 36 Patents

IBM: 36 patents #2,703 of 70,183Top 4%
Wappingers Falls, NY: #49 of 884 inventorsTop 6%
New York: #3,106 of 115,490 inventorsTop 3%
Overall (All Time): #92,222 of 4,157,543Top 3%
36 Patents All Time
Debjit Sinha has been granted 36 US patents while listed as an inventor at IBM. The first was granted in 2010 and the most recent in August 2021. Debjit Sinha ranks #92,222 of 4,157,543 US inventors in our database (top 2.2%). Patent records list Debjit Sinha in Wappingers Falls, NY, US.

Issued Patents All Time

Showing 1–25 of 36 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11093675 Statistical timing analysis considering multiple-input switching Vasant Rao, Michael H. Wood 2021-08-17 $3,119,000
11017137 Efficient projection based adjustment evaluation in static timing analysis of integrated circuits Chaitanya Ravindra Peddawad, Jeffrey G. Hemmett, Jason D. Morsey, Steven E. Washburn, Peter C. Elmendorf +1 more 2021-05-25 $5,474,000
10970455 Apportionment aware hierarchical timing optimization Adil Bhanji, Nathaniel D. Hieter 2021-04-06 $3,234,000
10929567 Parallel access to running electronic design automation (EDA) application Kerim Kalafala, Douglas Keller, Richard W. Taggart, Natesan Venkateswaran 2021-02-23 $3,028,000
10831954 Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs Ravi Chander LEDALLA, Chaobo Li, Adil Bhanji, Gregory M. Schaeffer, Michael H. Wood 2020-11-10 $848,000
10747925 Variable accuracy incremental timing analysis Jeffrey G. Hemmett, Kerim Kalafala, Natesan Venkateswaran, Eric A. Foreman, Chaitanya Ravindra Peddawad 2020-08-18 $3,155,000
10387682 Parallel access to running electronic design automation (EDA) application Kerim Kalafala, Douglas Keller, Richard W. Taggart, Natesan Venkateswaran 2019-08-20 $1,949,000
10380286 Multi-sided variations for creating integrated circuits Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala +4 more 2019-08-13 $1,909,000
10380289 Multi-sided variations for creating integrated circuits Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala +4 more 2019-08-13 $1,909,000
10346569 Multi-sided variations for creating integrated circuits Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala +4 more 2019-07-09 $2,201,000
10325059 Incremental common path pessimism analysis Tsung-Wei Huang, Kerim Kalafala, Vasant Rao, Natesan Venkateswaran 2019-06-18 $3,033,000
10169527 Accurate statistical timing for boundary gates of hierarchical timing models Hemlata Gupta, Chandramouli Visweswariah 2019-01-01
9940431 Accurate statistical timing for boundary gates of hierarchical timing models Hemlata Gupta, Chandramouli Visweswariah 2018-04-10 $2,135,000
9916405 Distributed timing analysis of a partitioned integrated circuit design Tsung-Wei Huang, Kerim Kalafala, Natesan Venkateswaran 2018-03-13 $2,527,000
9836572 Incremental common path pessimism analysis Tsung-Wei Huang, Kerim Kalafala, Vasant Rao, Natesan Venkateswaran 2017-12-05 $3,039,000
9798843 Statistical timing using macro-model considering statistical timing value entry Jin Hu, SheshaShayee K. Raghunathan, Vladimir Zolotov 2017-10-24 $3,030,000
9710594 Variation-aware timing analysis using waveform construction Kerim Kalafala, SheshaShayee K. Raghunathan, Michael H. Wood, Vladimir Zolotov 2017-07-18 $2,009,000
9690899 Prioritized path tracing in statistical timing analysis of integrated circuits Vasant Rao, Chandramouli Visweswariah 2017-06-27 $2,603,000
9659121 Deterministic and statistical timing modeling for differential circuits Hemlata Gupta, Jin Hu, Chad Andrew Marquart, Vasant Rao 2017-05-23 $2,171,000
9607124 Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints Adil Bhanji, Kerim Kalafala, Ravichander Ledalla, Chandramouli Visweswariah, Michael H. Wood 2017-03-28 $2,520,000
9400864 System and method for maintaining slack continuity in incremental statistical timing analysis David J. Hathaway, Jeffrey G. Hemmett, Kerim Kalafala 2016-07-26 $5,666,000
9342639 Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions Christine T. Casey, Kerim Kalafala, Ravichander Ledalla 2016-05-17 $3,602,000
8930864 Method of sharing and re-using timing models in a chip across multiple voltage domains Eric Jason Fluhr, Stephen G. Shuma, Natesan Venkateswaran, Chandramouli Visweswariah, Michael H. Wood +1 more 2015-01-06 $2,134,000
8732642 Method for achieving an efficient statistical optimization of integrated circuits Chandramouli Visweswariah, Eric Jason Fluhr, Stephen G. Shuma, Michael H. Wood 2014-05-20 $10,035,000
8683409 Performing statistical timing analysis with non-separable statistical and deterministic variations Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov 2014-03-25 $4,381,000