| 11288425 |
Path-based timing driven placement using iterative pseudo netlist changes |
Benjamin Neil Trombley, Daniel Arthur Gay |
2022-03-29 |
| 11030367 |
Out-of-context feedback hierarchical large block synthesis (HLBS) optimization |
Frank J. Musante, Alexander J. Suess, Ofer Geva |
2021-06-08 |
| 10970447 |
Leverage cycle stealing within optimization flows |
Kerim Kalafala, Alexander J. Suess |
2021-04-06 |
| 10970455 |
Apportionment aware hierarchical timing optimization |
Debjit Sinha, Adil Bhanji |
2021-04-06 |
| 10552562 |
Leverage cycle stealing within optimization flows |
Kerim Kalafala, Alexander J. Suess |
2020-02-04 |
| 10540465 |
Leverage cycle stealing within optimization flows |
Kerim Kalafala, Alexander J. Suess |
2020-01-21 |
| 10216875 |
Leverage cycle stealing within optimization flows |
Kerim Kalafala, Alexander J. Suess |
2019-02-26 |
| 10210297 |
Optimizing placement of circuit resources using a globally accessible placement memory |
David J. Hathaway, Shyam Ramji, Alexander J. Suess |
2019-02-19 |
| 9785735 |
Parallel incremental global routing |
Paul M. Campbell, Douglas Keller, Adam P. Matheny, Alexander J. Suess |
2017-10-10 |
| 9747400 |
Optimizing placement of circuit resources using a globally accessible placement memory |
David J. Hathaway, Shyam Ramji, Alexander J. Suess |
2017-08-29 |
| 9703914 |
Optimizing placement of circuit resources using a globally accessible placement memory |
David J. Hathaway, Shyam Ramji, Alexander J. Suess |
2017-07-11 |
| 9639654 |
Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit |
Bijian Chen, David J. Hathaway, Kerim Kalafala, Jeffrey S. Piaget, Alexander J. Suess |
2017-05-02 |
| 9436791 |
Optimizing placement of circuit resources using a globally accessible placement memory |
David J. Hathaway, Shyam Ramji, Alexander J. Suess |
2016-09-06 |
| 9418188 |
Optimizing placement of circuit resources using a globally accessible placement memory |
David J. Hathaway, Shyam Ramji, Alexander J. Suess |
2016-08-16 |
| 8302049 |
Method for enabling multiple incompatible or costly timing environment for efficient timing closure |
Frank J. Musante, William E. Dougherty, Jr., Alexander J. Suess |
2012-10-30 |
| 8234612 |
Cone-aware spare cell placement using hypergraph connectivity analysis |
Benjiman L. Goodman, Jeremy T. Hopkins, Samuel I. Ward |
2012-07-31 |
| 7500207 |
Influence-based circuit design |
Subhrajit Bhattacharya, Anthony Correale, Jr., Veena S. Pureswaran, Ruchir Puri |
2009-03-03 |
| 7178120 |
Method for performing timing closure on VLSI chips in a distributed environment |
David J. Hathaway, Prabhakar Kudva, David S. Kung, Leon Stok |
2007-02-13 |
| 5877965 |
Parallel hierarchical timing correction |
Charles Kenneth Hines, Todd E. Leonard, Peter J. Osler |
1999-03-02 |
