Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11983477 | Routing layer re-optimization in physical synthesis | Lakshmi N. Reddy, Ying Zhou, Cindy S. Washburn | 2024-05-14 |
| 11916384 | Region-based power grid generation through modification of an initial power grid based on timing analysis | David Wolpert, Basanth Jagannathan, Michael H. Wood, Leon Sigal, James Leland +2 more | 2024-02-27 |
| 11080443 | Memory element graph-based placement in integrated circuit design | Myung-Chul Kim, Arjen A. Mets, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy +2 more | 2021-08-03 |
| 11030367 | Out-of-context feedback hierarchical large block synthesis (HLBS) optimization | Frank J. Musante, Nathaniel D. Hieter, Ofer Geva | 2021-06-08 |
| 10970447 | Leverage cycle stealing within optimization flows | Nathaniel D. Hieter, Kerim Kalafala | 2021-04-06 |
| 10902167 | Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits | Chaitanya Ravindra Peddawad, Kerim Kalafala, Hemlata Gupta, Gregory M. Schaeffer | 2021-01-26 |
| 10776543 | Automated region based optimization of chip manufacture | Josiah Hamilton, David J. Geiger, Mihir Choudhury | 2020-09-15 |
| 10755017 | Cell placement in a circuit with shared inputs and outputs | Brent A. Anderson, Laura R. Darden, Albert M. Chu | 2020-08-25 |
| 10706194 | Boundary assertion-based power recovery in integrated circuit design | Cindy S. Washburn | 2020-07-07 |
| 10606970 | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma +3 more | 2020-03-31 |
| 10558775 | Memory element graph-based placement in integrated circuit design | Myung-Chul Kim, Arjen A. Mets, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy +2 more | 2020-02-11 |
| 10552562 | Leverage cycle stealing within optimization flows | Nathaniel D. Hieter, Kerim Kalafala | 2020-02-04 |
| 10540465 | Leverage cycle stealing within optimization flows | Nathaniel D. Hieter, Kerim Kalafala | 2020-01-21 |
| 10216875 | Leverage cycle stealing within optimization flows | Nathaniel D. Hieter, Kerim Kalafala | 2019-02-26 |
| 10210297 | Optimizing placement of circuit resources using a globally accessible placement memory | David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji | 2019-02-19 |
| 10013516 | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma +3 more | 2018-07-03 |
| 9922149 | Integration of functional analysis and common path pessimism removal in static timing analysis | Peter C. Elmendorf, Kerim Kalafala, Stephen G. Shuma | 2018-03-20 |
| 9785735 | Parallel incremental global routing | Paul M. Campbell, Nathaniel D. Hieter, Douglas Keller, Adam P. Matheny | 2017-10-10 |
| 9785737 | Parallel multi-threaded common path pessimism removal in multiple paths | David J. Hathaway, Kerim Kalafala, Vasant Rao, Vladimir Zolotov | 2017-10-10 |
| 9747400 | Optimizing placement of circuit resources using a globally accessible placement memory | David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji | 2017-08-29 |
| 9703914 | Optimizing placement of circuit resources using a globally accessible placement memory | David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji | 2017-07-11 |
| 9646122 | Variable accuracy parameter modeling in statistical timing | Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma +2 more | 2017-05-09 |
| 9639654 | Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit | Bijian Chen, David J. Hathaway, Nathaniel D. Hieter, Kerim Kalafala, Jeffrey S. Piaget | 2017-05-02 |
| 9501609 | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shurma +3 more | 2016-11-22 |
| 9483604 | Variable accuracy parameter modeling in statistical timing | Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma +2 more | 2016-11-01 |