Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
OG

Ofer Geva — 12 Patents

IBM: 11 patents #10,022 of 70,183Top 15%
General Motors: 1 patents #9,441 of 18,328Top 55%
Poughkeepsie, NY: #327 of 1,613 inventorsTop 25%
New York: #12,442 of 115,490 inventorsTop 15%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Ofer Geva has been granted 12 US patents while listed as an inventor at IBM. The first was granted in 2019 and the most recent in July 2025. Ofer Geva ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Ofer Geva in Poughkeepsie, NY, US.

Patents per Year

Patents granted per year, 2019 to 2025Bar chart with a peak of 5 patents in 2020.peak 52019: 1 patents20192020: 5 patents20202021: 2 patents20212022: 1 patents20222023: 2 patents20232025: 1 patents2025

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12367331 Approach to child block pinning Jesse Peter Surprise, Eduard Herkel, Faisal Hasan 2025-07-22
11797740 Even apportionment based on positive timing slack threshold Jesse Peter Surprise, Eduard Herkel, Michael H. Wood, Chris Aaron Cavitt, Tsz-Mei Ko 2023-10-24 $9,282,000
11775730 Hierarchical large block synthesis (HLBS) filling Brittany Duffy, Timothy A. Schell, Eduard Herkel, Jesse Peter Surprise 2023-10-03 $6,984,000
11296093 Deep trench capacitor distribution Asaf Regev, Christopher J. Berry, Amit Amos Atias, Timothy A. Schell 2022-04-05 $5,706,000
11030367 Out-of-context feedback hierarchical large block synthesis (HLBS) optimization Frank J. Musante, Nathaniel D. Hieter, Alexander J. Suess 2021-06-08 $4,452,000
10997737 Method and system for aligning image data from a vehicle camera Michael Slutsky 2021-05-04 $40,166,000
10831958 Integrated circuit design with optimized timing constraint configuration Shiran Raz, Yaniv Maroz 2020-11-10 $848,000
10657211 Circuit generation based on zero wire load assertions Limor Plotkin, Shiran Raz, Yaniv Maroz 2020-05-19 $2,035,000
10572613 Estimating timing convergence using assertion comparisons Yaniv Maroz, Limor Plotkin, Shiran Raz 2020-02-25 $1,919,000
10568203 Modifying a circuit design Shiran Raz, Limor Elizov, Yaniv Maroz 2020-02-18 $2,353,000
10546092 Modifying a circuit design based on pre-routed top level design Ido Geldman, Rina Kipnis, Vadim Liberchuk, Yaniv Maroz, Asaf Regev 2020-01-28 $1,679,000
10325045 Estimating timing convergence using assertion comparisons Yaniv Maroz, Limor Plotkin, Shiran Raz 2019-06-18 $3,033,000