Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367331 | Approach to child block pinning | Jesse Peter Surprise, Eduard Herkel, Faisal Hasan | 2025-07-22 |
| 11797740 | Even apportionment based on positive timing slack threshold | Jesse Peter Surprise, Eduard Herkel, Michael H. Wood, Chris Aaron Cavitt, Tsz-Mei Ko | 2023-10-24 |
| 11775730 | Hierarchical large block synthesis (HLBS) filling | Brittany Duffy, Timothy A. Schell, Eduard Herkel, Jesse Peter Surprise | 2023-10-03 |
| 11296093 | Deep trench capacitor distribution | Asaf Regev, Christopher J. Berry, Amit Amos Atias, Timothy A. Schell | 2022-04-05 |
| 11030367 | Out-of-context feedback hierarchical large block synthesis (HLBS) optimization | Frank J. Musante, Nathaniel D. Hieter, Alexander J. Suess | 2021-06-08 |
| 10997737 | Method and system for aligning image data from a vehicle camera | Michael Slutsky | 2021-05-04 |
| 10831958 | Integrated circuit design with optimized timing constraint configuration | Shiran Raz, Yaniv Maroz | 2020-11-10 |
| 10657211 | Circuit generation based on zero wire load assertions | Limor Plotkin, Shiran Raz, Yaniv Maroz | 2020-05-19 |
| 10572613 | Estimating timing convergence using assertion comparisons | Yaniv Maroz, Limor Plotkin, Shiran Raz | 2020-02-25 |
| 10568203 | Modifying a circuit design | Shiran Raz, Limor Elizov, Yaniv Maroz | 2020-02-18 |
| 10546092 | Modifying a circuit design based on pre-routed top level design | Ido Geldman, Rina Kipnis, Vadim Liberchuk, Yaniv Maroz, Asaf Regev | 2020-01-28 |
| 10325045 | Estimating timing convergence using assertion comparisons | Yaniv Maroz, Limor Plotkin, Shiran Raz | 2019-06-18 |