Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12282721 | Netlist design for post silicon local clock controller timing improvement | Michael A. Kazda, Sean Michael Carey, Michael H. Wood | 2025-04-22 |
| 11030367 | Out-of-context feedback hierarchical large block synthesis (HLBS) optimization | Nathaniel D. Hieter, Alexander J. Suess, Ofer Geva | 2021-06-08 |
| 10216882 | Critical path straightening system based on free-space aware and timing driven incremental placement | Jinwook Jung, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy, Gustavo E. Tellez +1 more | 2019-02-26 |
| 9075948 | Method of improving timing critical cells for physical design in the presence of local placement congestion | Michael A. Kazda, Alexander J. Suess | 2015-07-07 |
| 8392866 | Task-based multi-process design synthesis with notification of transform signatures | Anthony D. Drumm, Jagannathan Narasimhan, Louise H. Trevillyan | 2013-03-05 |
| 8302049 | Method for enabling multiple incompatible or costly timing environment for efficient timing closure | William E. Dougherty, Jr., Nathaniel D. Hieter, Alexander J. Suess | 2012-10-30 |
| 7996812 | Method of minimizing early-mode violations causing minimum impact to a chip design | Pooja M. Kotecha, Veena S. Pureswaran, Louise H. Trevillyan, Paul G. Villarrubia | 2011-08-09 |