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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Anthony D. Drumm — 19 Patents

IBM: 19 patents #5,793 of 70,183Top 9%
Endwell, NY: #14 of 267 inventorsTop 6%
New York: #7,469 of 115,490 inventorsTop 7%
Overall (All Time): #229,345 of 4,157,543Top 6%
19 Patents All Time
Anthony D. Drumm has been granted 19 US patents while listed as an inventor at IBM. The first was granted in 1991 and the most recent in March 2014. Anthony D. Drumm ranks #229,345 of 4,157,543 US inventors in our database (top 5.5%). Patent records list Anthony D. Drumm in Endwell, NY, US.

Patents per Year

Patents granted per year, 1991 to 2014Bar chart with a peak of 3 patents in 1998.peak 31991: 2 patents19911995: 1 patents1996: 2 patents19961998: 3 patents2002: 1 patents20022003: 2 patents2004: 1 patents20042007: 1 patents2008: 1 patents20082011: 1 patents2012: 1 patents20122013: 2 patents2014: 1 patents2014

Issued Patents All Time

Showing 1–19 of 19 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8677304 Task-based multi-process design synthesis Jagannathan Narasimhan, Lakshmi N. Reddy, Louise H. Trevillyan, Brian C. Wilson 2014-03-18 $3,993,000
8407652 Task-based multi-process design synthesis Jagannathan Narasimhan, Lakshmi N. Reddy, Louise H. Trevillyan, Brian C. Wilson 2013-03-26 $5,395,000
8392866 Task-based multi-process design synthesis with notification of transform signatures Frank J. Musante, Jagannathan Narasimhan, Louise H. Trevillyan 2013-03-05 $6,102,000
8341565 Task-based multi-process design synthesis with reproducible transforms Jagannathan Narasimhan, Lakshmi N. Reddy, Louise H. Trevillyan 2012-12-25
7900182 Method and system for designing an electronic circuit Lakshmi N. Reddy, Louise H. Trevillyan 2011-03-01 $4,705,000
7451416 Method and system for designing an electronic circuit Lakshmi N. Reddy, Louise H. Trevillyan 2008-11-11 $10,353,000
7168057 Targeted optimization of buffer-tree logic Brian C. Wilson 2007-01-23 $10,875,000
6826740 Automated buffer insertion incorporating congestion relief for use in connection with physical design of integrated circuit 2004-11-30 $6,459,000
6643683 Interactive client-server environment for performing collaborative timing analysis of circuit designs Mark S. Fredrickson, Marcus Matthew Poplawski, Brian C. Wilson 2003-11-04 $11,371,000
6601223 System and method for fast interconnect delay estimation through iterative refinement Ruchir Puri, David S. Kung 2003-07-29 $10,466,000
6425110 Incremental design tuning and decision mediator David J. Hathaway, Peter J. Osler 2002-07-23 $13,664,000
5825661 Method and apparatus for automatic post-layout optimization of an integrated circuit 1998-10-20 $18,639,000
5799170 Simplified buffer manipulation using standard repowering function Robert L. Kanzelman, Bruce George Rudolph 1998-08-25 $17,258,000
5761079 Engineering change management system employing a smart editor 1998-06-02 $5,806,000
5537330 Method for mapping in logic synthesis by logic classification Robert F. Damiano, Michael Kay Edwards, Robert L. Kanzelman, Kathy M. McCarthy 1996-07-16 $6,072,000
5508937 Incremental timing analysis Richard P. Abato, David J. Hathaway, Lukas Paul Pieter Pepijn Van Ginneken 1996-04-16 $11,483,000
5436849 Incremental logic synthesis system for efficient revision of logic circuit designs 1995-07-25 $11,735,000
5029102 Logical synthesis Charles P. Sweet 1991-07-02 $16,319,000
5003487 Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis Randall C. Itskin, Kenneth W. Todd 1991-03-26 $18,949,000