Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8677304 | Task-based multi-process design synthesis | Jagannathan Narasimhan, Lakshmi N. Reddy, Louise H. Trevillyan, Brian C. Wilson | 2014-03-18 |
| 8407652 | Task-based multi-process design synthesis | Jagannathan Narasimhan, Lakshmi N. Reddy, Louise H. Trevillyan, Brian C. Wilson | 2013-03-26 |
| 8392866 | Task-based multi-process design synthesis with notification of transform signatures | Frank J. Musante, Jagannathan Narasimhan, Louise H. Trevillyan | 2013-03-05 |
| 8341565 | Task-based multi-process design synthesis with reproducible transforms | Jagannathan Narasimhan, Lakshmi N. Reddy, Louise H. Trevillyan | 2012-12-25 |
| 7900182 | Method and system for designing an electronic circuit | Lakshmi N. Reddy, Louise H. Trevillyan | 2011-03-01 |
| 7451416 | Method and system for designing an electronic circuit | Lakshmi N. Reddy, Louise H. Trevillyan | 2008-11-11 |
| 7168057 | Targeted optimization of buffer-tree logic | Brian C. Wilson | 2007-01-23 |
| 6826740 | Automated buffer insertion incorporating congestion relief for use in connection with physical design of integrated circuit | — | 2004-11-30 |
| 6643683 | Interactive client-server environment for performing collaborative timing analysis of circuit designs | Mark S. Fredrickson, Marcus Matthew Poplawski, Brian C. Wilson | 2003-11-04 |
| 6601223 | System and method for fast interconnect delay estimation through iterative refinement | Ruchir Puri, David S. Kung | 2003-07-29 |
| 6425110 | Incremental design tuning and decision mediator | David J. Hathaway, Peter J. Osler | 2002-07-23 |
| 5825661 | Method and apparatus for automatic post-layout optimization of an integrated circuit | — | 1998-10-20 |
| 5799170 | Simplified buffer manipulation using standard repowering function | Robert L. Kanzelman, Bruce George Rudolph | 1998-08-25 |
| 5761079 | Engineering change management system employing a smart editor | — | 1998-06-02 |
| 5537330 | Method for mapping in logic synthesis by logic classification | Robert F. Damiano, Michael Kay Edwards, Robert L. Kanzelman, Kathy M. McCarthy | 1996-07-16 |
| 5508937 | Incremental timing analysis | Richard P. Abato, David J. Hathaway, Lukas Paul Pieter Pepijn Van Ginneken | 1996-04-16 |
| 5436849 | Incremental logic synthesis system for efficient revision of logic circuit designs | — | 1995-07-25 |
| 5029102 | Logical synthesis | Charles P. Sweet | 1991-07-02 |
| 5003487 | Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis | Randall C. Itskin, Kenneth W. Todd | 1991-03-26 |