Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8495547 | Providing secondary power pins in integrated circuit design | Joachim Keinert, Douglass T. Lamb | 2013-07-23 |
| 6829755 | Variable detail automatic invocation of transistor level timing for application specific integrated circuit static timing analysis | Paul Gutwin | 2004-12-07 |
| 6795951 | Method and system for fault-tolerant static timing analysis | David J. Hathaway | 2004-09-21 |
| 6588000 | Method of partitioning large transistor design to facilitate transistor level timing | Paul Gutwin | 2003-07-01 |
| 6425110 | Incremental design tuning and decision mediator | David J. Hathaway, Anthony D. Drumm | 2002-07-23 |
| 6023567 | Method and apparatus for verifying timing rules for an integrated circuit design | Tad J. Wilder, Charles B. Winn | 2000-02-08 |
| 5877965 | Parallel hierarchical timing correction | Nathaniel D. Hieter, Charles Kenneth Hines, Todd E. Leonard | 1999-03-02 |
| 5099415 | Guess mechanism for virtual address translation | Fred Tze-Keung Tong | 1992-03-24 |