Peter J. Osler — 8 Patents at IBM

Peter J. Osler has been granted 8 US patents while listed as an inventor at IBM. The first was granted in 1992 and the most recent in July 2013. Peter J. Osler ranks #600,572 of 4,157,543 US inventors in our database (top 14.4%). Patent records list Peter J. Osler in Jericho, VT, US.

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
8495547	Providing secondary power pins in integrated circuit design	Joachim Keinert, Douglass T. Lamb	2013-07-23	$2,085,000
6829755	Variable detail automatic invocation of transistor level timing for application specific integrated circuit static timing analysis	Paul Gutwin	2004-12-07	$6,343,000
6795951	Method and system for fault-tolerant static timing analysis	David J. Hathaway	2004-09-21	$8,100,000
6588000	Method of partitioning large transistor design to facilitate transistor level timing	Paul Gutwin	2003-07-01	$13,647,000
6425110	Incremental design tuning and decision mediator	David J. Hathaway, Anthony D. Drumm	2002-07-23	$13,664,000
6023567	Method and apparatus for verifying timing rules for an integrated circuit design	Tad J. Wilder, Charles B. Winn	2000-02-08	$33,742,000
5877965	Parallel hierarchical timing correction	Nathaniel D. Hieter, Charles Kenneth Hines, Todd E. Leonard	1999-03-02	$11,544,000
5099415	Guess mechanism for virtual address translation	Fred Tze-Keung Tong	1992-03-24	$12,540,000

Peter J. Osler — 8 Patents

Issued Patents All Time

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