Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8306802 | Method for modeling an HDL design using symbolic simulation | Yunshan Zhu, James H. Kukula, Joseph T. Buck | 2012-11-06 |
| 7904867 | Integrating a boolean SAT solver into a router | Jerry R. Burch, Pei-Hsin Ho, James H. Kukula | 2011-03-08 |
| 7254793 | Latch modeling technique for formal verification | Yirng-An Chen, Bharat Kalyanpur, James H. Kukula | 2007-08-07 |
| 7130783 | Simulation-based functional verification of microcircuit designs | Kevin M. Harer, Pei-Hsin Ho | 2006-10-31 |
| 7107553 | Method and apparatus for solving constraints | Brian Lockyear, James H. Kukula, Carl Preston Pixley | 2006-09-12 |
| 6397169 | Adaptive cell separation and circuit changes driven by maximum capacitance rules | Narendra V. Shenoy, Hi-Keung Tony Ma, Mahesh A. Iyer, Kevin M. Harer | 2002-05-28 |
| 5754824 | Logic synthesis for logic array modules | Ilan Spillinger, Louise H. Trevillyan, Lukas Paul Pieter Pepijn Van Ginneken | 1998-05-19 |
| 5537330 | Method for mapping in logic synthesis by logic classification | Anthony D. Drumm, Michael Kay Edwards, Robert L. Kanzelman, Kathy M. McCarthy | 1996-07-16 |