Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7904867 | Integrating a boolean SAT solver into a router | Robert F. Damiano, Pei-Hsin Ho, James H. Kukula | 2011-03-08 |
| 7836414 | Formally proving the functional equivalence of pipelined designs containing memories | Alfred Koelbl, Carl Preston Pixley | 2010-11-16 |
| 7389479 | Formally proving the functional equivalence of pipelined designs containing memories | Alfred Koelbl, Carl Preston Pixley | 2008-06-17 |
| 6308299 | Method and system for combinational verification having tight integration of verification techniques | Vigyan Singhal | 2001-10-23 |
| 6247163 | Method and system of latch mapping for combinational equivalence checking | Vigyan Singhal | 2001-06-12 |