Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8306802 | Method for modeling an HDL design using symbolic simulation | Yunshan Zhu, Robert F. Damiano, Joseph T. Buck | 2012-11-06 |
| 7904867 | Integrating a boolean SAT solver into a router | Jerry R. Burch, Robert F. Damiano, Pei-Hsin Ho | 2011-03-08 |
| 7890894 | Phase abstraction for formal verification | Per M. Bjesse | 2011-02-15 |
| 7343575 | Phase abstraction for formal verification | Per M. Bjesse | 2008-03-11 |
| 7257786 | Method and apparatus for solving constraints | — | 2007-08-14 |
| 7254793 | Latch modeling technique for formal verification | Yirng-An Chen, Robert F. Damiano, Bharat Kalyanpur | 2007-08-07 |
| 7149987 | Method and apparatus for performing generator-based verification | Yunshan Zhu | 2006-12-12 |
| 7107553 | Method and apparatus for solving constraints | Brian Lockyear, Robert F. Damiano, Carl Preston Pixley | 2006-09-12 |
| 7092858 | Method and apparatus for formally constraining random simulation | Thomas R. Shiple, Rajeev Ranjan | 2006-08-15 |
| 6059837 | Method and system for automata-based approach to state reachability of interacting extended finite state machines | Thomas R. Shiple | 2000-05-09 |
| 5418961 | Parallel tables for data model with inheritance | Richard Segal | 1995-05-23 |
| 4736319 | Interrupt mechanism for multiprocessing system having a plurality of interrupt lines in both a global bus and cell buses | Sumit DasGupta, John M. Hancock, Roger E. Peo | 1988-04-05 |