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2019-06-18 |
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Equivalence checking between two or more circuit designs that include square root circuits |
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Elimination of illegal states within equivalence checking |
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2016-11-22 |
| 9189581 |
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Himanshu Jain |
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Equivalence checking using structural analysis on data flow graphs |
Sudipta Kundu |
2014-12-16 |
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Formal verification of bit-serial division and bit-serial square-root circuit designs |
Himanshu Jain |
2014-05-20 |
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Alfred Koelbl |
2013-11-19 |
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Method and apparatus for performing formal verification using data-flow graphs |
Alfred Koelbl |
2011-12-13 |
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Method and apparatus for formally checking equivalence using equivalence relationships |
Alfred Koelbl |
2011-08-16 |
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2010-11-16 |
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Alfred Koelbl |
2009-04-21 |
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Alfred Koelbl |
2009-03-24 |
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Method and apparatus for performing formal verification using data-flow graphs |
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2009-03-24 |
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Formally proving the functional equivalence of pipelined designs containing memories |
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2008-06-17 |
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2008-06-10 |
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Alfred Koelbl |
2007-08-21 |
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2006-09-12 |
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2001-11-20 |
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Method for performing model checking in integrated circuit design |
Matthew Kaufmann, Andrew K. Martin |
1999-12-07 |
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Method for determining functional equivalence between design models |
Jaehong Park |
1998-05-19 |
| 5680332 |
Measurement of digital circuit simulation test coverage utilizing BDDs and state bins |
Richard Raimi |
1997-10-21 |
| 5638381 |
Apparatus and method for deriving correspondence between storage elements of a first circuit model and storage elements of a second circuit model |
Hyunwoo Cho |
1997-06-10 |
| 5572535 |
Method and data processing system for verifying the correct operation of a tri-state multiplexer in a circuit design |
Hyunwoo Cho, Bernard Plessier, Jesse R. Wilson, Ralph McGarity |
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Apparatus and method for determining sequential hardware equivalence |
— |
1994-07-19 |
