Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8677304 | Task-based multi-process design synthesis | Anthony D. Drumm, Jagannathan Narasimhan, Lakshmi N. Reddy, Brian C. Wilson | 2014-03-18 |
| 8539400 | Routability using multiplexer structures | Charles J. Alpert, Victor N. Kravets, Zhuo Li, Ying Zhou | 2013-09-17 |
| 8407652 | Task-based multi-process design synthesis | Anthony D. Drumm, Jagannathan Narasimhan, Lakshmi N. Reddy, Brian C. Wilson | 2013-03-26 |
| 8392866 | Task-based multi-process design synthesis with notification of transform signatures | Anthony D. Drumm, Frank J. Musante, Jagannathan Narasimhan | 2013-03-05 |
| 8341565 | Task-based multi-process design synthesis with reproducible transforms | Anthony D. Drumm, Jagannathan Narasimhan, Lakshmi N. Reddy | 2012-12-25 |
| 8271920 | Converged large block and structured synthesis for high performance microprocessor designs | Minsik Cho, Victor N. Kravets, Smita Krishnaswamy, Dorothy Kucar, Jagannathan Narasimhan +6 more | 2012-09-18 |
| 8020134 | Method and apparatus for parallel processing of semiconductor chip designs | Michael W. Dotson, Anthony DeGroff Drumm, Dazhuang J. Ma, Ruchir Puri | 2011-09-13 |
| 7996812 | Method of minimizing early-mode violations causing minimum impact to a chip design | Pooja M. Kotecha, Frank J. Musante, Veena S. Pureswaran, Paul G. Villarrubia | 2011-08-09 |
| 7930669 | Stage mitigation of interconnect variability | Mark A. Lavin, Ruchir Puri, Hua Xiang | 2011-04-19 |
| 7900182 | Method and system for designing an electronic circuit | Anthony D. Drumm, Lakshmi N. Reddy | 2011-03-01 |
| 7895556 | Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes | Pooja M. Kotecha, David J. Hathaway | 2011-02-22 |
| 7685553 | System and method for global circuit routing incorporating estimation of critical area estimate metrics | Evanthia Papadopoulou, Ruchir Puri, Mervyn Y. Tan, Hua Xiang | 2010-03-23 |
| 7581201 | System and method for sign-off timing closure of a VLSI chip | Michael A. Kazda, Pooja M. Kotecha, Adam P. Matheny, Lakshmi N Reddy, Paul G. Villarrubia | 2009-08-25 |
| 7451416 | Method and system for designing an electronic circuit | Anthony D. Drumm, Lakshmi N. Reddy | 2008-11-11 |
| 7448014 | Design stage mitigation of interconnect variability | Mark A. Lavin, Ruchir Puri, Hua Xiang | 2008-11-04 |
| 7225421 | Clock tree distribution generation by determining allowed placement regions for clocked elements | William R. Migatz, Paul M. Campbell, David J. Hathaway, David S. Kung, Ruchir Puri | 2007-05-29 |
| 6958545 | Method for reducing wiring congestion in a VLSI chip design | Pooja M. Kotecha, Rama Gopal Gandham, Ruchir Puri, Adam P. Matheny | 2005-10-25 |
| 6698003 | Framework for multiple-engine based verification tools for integrated circuits | Jason R. Baumgartner, Geert Janssen, Andreas Kuehlmann, Viresh Paruthi | 2004-02-24 |
| 5754824 | Logic synthesis for logic array modules | Robert F. Damiano, Ilan Spillinger, Lukas Paul Pieter Pepijn Van Ginneken | 1998-05-19 |
| 5257201 | Method to efficiently reduce the number of connections in a circuit | Charles L. Berman | 1993-10-26 |