Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7127696 | Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management | Charles J. Alpert, Milos Hrkic, Stephen T. Quay | 2006-10-24 |
| 7065730 | Porosity aware buffered steiner tree construction | Charles J. Alpert, Jiang Hu, Stephen T. Quay | 2006-06-20 |
| 6958545 | Method for reducing wiring congestion in a VLSI chip design | Pooja M. Kotecha, Ruchir Puri, Louise H. Trevillyan, Adam P. Matheny | 2005-10-25 |
| 6915496 | Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique | Charles J. Alpert, Chong-Nuen Chu, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap +1 more | 2005-07-05 |
| 6898774 | Buffer insertion with adaptive blockage avoidance | Charles J. Alpert, Jiang Hu, Stephen T. Quay | 2005-05-24 |
| 6591411 | Apparatus and method for determining buffered steiner trees for complex circuits | Charles J. Alpert, Jiang Hu, Stephen T. Quay, Andrew J. Sullivan | 2003-07-08 |
| 6560752 | Apparatus and method for buffer library selection for use in buffer insertion | Charles J. Alpert, Jose L. Neves, Stephen T. Quay | 2003-05-06 |
| 6401234 | Method and system for re-routing interconnects within an integrated circuit design having blockages and bays | Charles J. Alpert, Jiang Hu, Jose L. Neves, Stephen T. Quay | 2002-06-04 |