Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10949884 | Ephemeral geofence campaign system | Andrew B. Cornwall, Lisa Seacat DeLuca, Nicholas R. Sandonato | 2021-03-16 |
| 10417663 | Ephemeral geofence campaign system | Andrew B. Cornwall, Lisa Seacat DeLuca, Nicholas R. Sandonato | 2019-09-17 |
| 10168857 | Virtual reality for cognitive messaging | Feras N. Y. Alnatsheh, Lisa Seacat DeLuca | 2019-01-01 |
| 7996812 | Method of minimizing early-mode violations causing minimum impact to a chip design | Frank J. Musante, Veena S. Pureswaran, Louise H. Trevillyan, Paul G. Villarrubia | 2011-08-09 |
| 7987440 | Method and system for efficient validation of clock skews during hierarchical static timing analysis | Kerim Kalafala, Jennifer E. Basile, David J. Hathaway | 2011-07-26 |
| 7895556 | Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes | David J. Hathaway, Louise H. Trevillyan | 2011-02-22 |
| 7581201 | System and method for sign-off timing closure of a VLSI chip | Michael A. Kazda, Adam P. Matheny, Lakshmi N Reddy, Louise H. Trevillyan, Paul G. Villarrubia | 2009-08-25 |
| 6958545 | Method for reducing wiring congestion in a VLSI chip design | Rama Gopal Gandham, Ruchir Puri, Louise H. Trevillyan, Adam P. Matheny | 2005-10-25 |