| 8020134 |
Method and apparatus for parallel processing of semiconductor chip designs |
Anthony DeGroff Drumm, Dazhuang J. Ma, Ruchir Puri, Louise H. Trevillyan |
2011-09-13 |
| 7934188 |
Legalization of VLSI circuit placement with blockages using hierarchical row slicing |
Charles J. Alpert, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan |
2011-04-26 |
| 7203916 |
System, method and program product for positioning I/O pads on a chip |
Matthew D. Wise |
2007-04-10 |
| 6263374 |
Apparatus for coupling a bus-based architecture to a switch network |
Howard Thomas Olnowich, James William Feeney, Michael Hans Fisher, John D. Jabusch, Robert Francis Lusch +1 more |
2001-07-17 |
| 5922063 |
Automatic hardware message header generator |
Howard Thomas Olnowich, James William Feeney, Robert Francis Lusch, Michael Anthony Maniguet |
1999-07-13 |
| 5742761 |
Apparatus for adapting message protocols for a switch network and a bus |
Howard Thomas Olnowich, James William Feeney, Michael Hans Fisher, John D. Jabusch, Robert Francis Lusch +1 more |
1998-04-21 |
