AK

Andreas Kuehlmann

CS Cadence Design Systems: 13 patents #76 of 2,263Top 4%
SY Synopsys: 5 patents #244 of 2,302Top 15%
IBM: 4 patents #21,733 of 70,183Top 35%
Overall (All Time): #169,182 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12387021 Using information flow for security aware design and analysis Jason K. Oberg, Alric Althoff 2025-08-12
10713069 Software and hardware emulation system Marat Boshernitsan, Scott McPeak, Roger H. Scott, Andy Chou, Kit Transue 2020-07-14
9836390 Static analysis of computer code to determine impact of change to a code component upon a dependent code component Marat Boshernitsan, Scott McPeak, Philip Chong, Tobias Welp 2017-12-05
9612943 Prioritization of tests of computer program code Marat Boshernitsan 2017-04-04
9317399 Policy evaluation based upon dynamic observation, static analysis and code change history Marat Boshernitsan, Scott McPeak, Roger H. Scott, Andy Chou, Kit Transue 2016-04-19
9032376 Static analysis of computer code to determine impact of change to a code component upon a dependent code component Marat Boshernitsan, Scott McPeak, Philip Chong, Tobias Welp 2015-05-12
8862439 General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software Kenneth L. McMillan, Shmuel Sagiv 2014-10-14
8656330 Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software Kenneth L. McMillan, Shmuel Sagiv 2014-02-18
8589845 Optimizing integrated circuit design through use of sequential timing information Christoph Albrecht, Philip Chong, Ellen Sentovich, Roberto Passerone 2013-11-19
8418101 Temporal decomposition for design and verification Xiaoqun Du 2013-04-09
8413090 Temporal decomposition for design and verification Xiaoqun Du 2013-04-02
8307316 Reducing critical cycle delay in an integrated circuit design through use of sequential slack Christoph Albrecht, Philip Chong, Ellen Sentovich, Roberto Passerone 2012-11-06
8020125 System, methods and apparatus for generation of simulation stimulus Nathan Boyd Kitchen 2011-09-13
7913210 Reducing critical cycle delay in an integrated circuit design through use of sequential slack Christoph Albrecht, Philip Chong, Ellen Sentovich, Roberto Passerone 2011-03-22
7900173 Temporal decomposition for design and verification Xiaoqun Du 2011-03-01
7743354 Optimizing integrated circuit design through use of sequential timing information Christoph Albrecht, Philip Chong, Ellen Sentovich, Roberto Passerone 2010-06-22
7624364 Data path and placement optimization in an integrated circuit through use of sequential timing information Christoph Albrecht, Philip Chong, Ellen Sentovich, Roberto Passerone 2009-11-24
7596770 Temporal decomposition for design and verification Xiaoqun Du 2009-09-29
7559040 Optimization of combinational logic synthesis through clock latency scheduling Christoph Albrecht, David John Seibert, Sascha Richter 2009-07-07
7296246 Multi-domain clock skew scheduling Kaushik Ravindran, Ellen Sentovich 2007-11-13
6698003 Framework for multiple-engine based verification tools for integrated circuits Jason R. Baumgartner, Geert Janssen, Viresh Paruthi, Louise H. Trevillyan 2004-02-24
6473884 Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis Malay Ganai, Geert Janssen, Florian Krohm, Viresh Paruthi 2002-10-29
6035107 Method for performing functional comparison of combinational circuits Florian Krohm 2000-03-07
5629858 CMOS transistor network to gate level model extractor for simulation, verification and test generation Sandip Kundu, Arvind Srinivasan 1997-05-13