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USPTO Patent Rankings Data through Dec 31, 2025
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Sandip Kundu — 13 Patents

Intel: 9 patents #4,462 of 30,777Top 15%
IBM: 4 patents #21,783 of 70,183Top 35%
Amherst, MA: #38 of 424 inventorsTop 9%
Massachusetts: #9,700 of 88,656 inventorsTop 15%
Overall (All Time): #362,438 of 4,157,543Top 9%
13 Patents All Time
Sandip Kundu has been granted 13 US patents while listed as an inventor at Intel. The first was granted in 1994 and the most recent in December 2016. Sandip Kundu ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Sandip Kundu in Amherst, MA, US.

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9520877 Apparatus and method for detecting or repairing minimum delay errors Pascal A. Meinerzhagen, James W. Tschanz, Vivek K. De 2016-12-13 $15,488,000
7197721 Weight compression/decompression system Srinivas Patil 2007-03-27 $11,700,000
7096397 Dft technique for avoiding contention/conflict in logic built-in self-test Sanjay Sengupta, Rajesh Galivanche 2006-08-22 $20,862,000
7036063 Generalized fault model for defects and circuit marginalities Sanjay Sengupta, Dhiraj Goswami 2006-04-25 $12,896,000
6973422 Method and apparatus for modeling and circuits with asynchronous behavior Sitaram Yadavalli 2005-12-06 $17,814,000
6938225 Scan design for double-edge-triggered flip-flops 2005-08-30 $19,986,000
6912701 Method and apparatus for power supply noise modeling and test pattern development 2005-06-28 $36,074,000
6715091 System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation 2004-03-30 $39,781,000
6510398 Constrained signature-based test Sanjay Sengupta, Rajesh Galivanche 2003-01-21 $41,003,000
5796751 Technique for sorting high frequency integrated circuits 1998-08-18 $11,146,000
5793777 System and method for testing internal nodes of an integrated circuit at any predetermined machine cycle 1998-08-11 $8,339,000
5629858 CMOS transistor network to gate level model extractor for simulation, verification and test generation Andreas Kuehlmann, Arvind Srinivasan 1997-05-13 $10,594,000
5297151 Adjustable weighted random test pattern generator for logic circuits Matthias Gruetzner, Leendert M. Huisman, Cordt Starke 1994-03-22 $7,732,000