Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 12413622 | System and method for generating cyber threat intelligence | Mahesh Banerjee | 2025-09-09 | |
| 7096397 | Dft technique for avoiding contention/conflict in logic built-in self-test | Sandip Kundu, Rajesh Galivanche | 2006-08-22 | $20,862,000 |
| 7036063 | Generalized fault model for defects and circuit marginalities | Sandip Kundu, Dhiraj Goswami | 2006-04-25 | $12,896,000 |
| 6510398 | Constrained signature-based test | Sandip Kundu, Rajesh Galivanche | 2003-01-21 | $41,003,000 |
| 6237121 | Method and apparatus for performing register transfer level scan selection | Sitaram Yadavalli | 2001-05-22 | $176,958,000 |