CA

Christoph Albrecht

CS Cadence Design Systems: 9 patents #141 of 2,263Top 7%
Google: 3 patents #8,000 of 22,993Top 35%
ZA Zahoransky Ag: 2 patents #6 of 25Top 25%
SA Sap Ag: 1 patents #1,847 of 3,812Top 50%
University of California: 1 patents #8,022 of 18,278Top 45%
📍 Todtnau, CA: #1 of 1 inventorsTop 100%
Overall (All Time): #274,395 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDate
10213014 Transfer station for transferring bristle filaments Ingo Kumpf, Florian Kiefer, Bernhard Rees 2019-02-26
9722912 Network stochastic cross-layer optimization for meeting traffic flow availability target at minimum cost Xiaoxue Zhao, Emilie Jeanne Anne Danna, Bikash Koley, Satyajeet Singh Ahuja, Vinayak Dangui 2017-08-01
9705773 Parallelized network traffic flow availability simulation using stochastic process and traffic engineering algorithms Xiaoxue Zhao, Emilie Jeanne Anne Danna, Alireza Ghaffarkhah, Ajay Kumar Bangla, Wenjie Jiang +2 more 2017-07-11
9687071 Tufting tool and brush making machine Robert Steinebrunner, Guido Sommer, Philipp Goldmann 2017-06-27
9128825 Optimizing allocation of flash memory to file groups Murray M. Stokely, Arif Merchant, Christian Eric Schrock, Xudong Shi 2015-09-08
8887110 Methods for designing intergrated circuits with automatically synthesized clock distribution networks Radu Zlatanovici, Saurabh Kumar Tiwary 2014-11-11
8589845 Optimizing integrated circuit design through use of sequential timing information Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone 2013-11-19
8307316 Reducing critical cycle delay in an integrated circuit design through use of sequential slack Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone 2012-11-06
8205182 Automatic synthesis of clock distribution networks Radu Zlatanovici, Saurabh Kumar Tiwary 2012-06-19
7945880 Constraint based retiming of synchronous circuits Sascha Richter 2011-05-17
7913210 Reducing critical cycle delay in an integrated circuit design through use of sequential slack Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone 2011-03-22
7743354 Optimizing integrated circuit design through use of sequential timing information Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone 2010-06-22
7739642 Optimizing integrated circuit design through balanced combinational slack plus sequential slack 2010-06-15
7624364 Data path and placement optimization in an integrated circuit through use of sequential timing information Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone 2009-11-24
7574689 Generic interface to provide object access display views based on object type Michael Igelbrink 2009-08-11
7559040 Optimization of combinational logic synthesis through clock latency scheduling Andreas Kuehlmann, David John Seibert, Sascha Richter 2009-07-07
7062743 Floorplan evaluation, global routing, and buffer insertion for integrated circuits Andrew B. Kahng, Ion Mandoiu, Alexander Z. Zelikovsky 2006-06-13