RZ

Radu Zlatanovici

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
📍 Oakland, CA: #1,186 of 4,380 inventorsTop 30%
🗺 California: #106,790 of 386,348 inventorsTop 30%
Overall (All Time): #1,003,538 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
9071238 Contention-free level converting flip-flops for low-swing clocking 2015-06-30
9018995 Integrated clock gating cell for circuits with double edge triggered flip-flops Kumar Subramani 2015-04-28
8887110 Methods for designing intergrated circuits with automatically synthesized clock distribution networks Christoph Albrecht, Saurabh Kumar Tiwary 2014-11-11
8341567 Boolean satisfiability based verification of analog circuits Saurabh Kumar Tiwary, Anubhav Gupta, Joel R. Phillips, Claudio Pinello 2012-12-25
8205182 Automatic synthesis of clock distribution networks Christoph Albrecht, Saurabh Kumar Tiwary 2012-06-19