RP

Roberto Passerone

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
Overall (All Time): #861,673 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8589845 Optimizing integrated circuit design through use of sequential timing information Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich 2013-11-19
8307316 Reducing critical cycle delay in an integrated circuit design through use of sequential slack Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich 2012-11-06
7913210 Reducing critical cycle delay in an integrated circuit design through use of sequential slack Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich 2011-03-22
7743354 Optimizing integrated circuit design through use of sequential timing information Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich 2010-06-22
7624364 Data path and placement optimization in an integrated circuit through use of sequential timing information Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich 2009-11-24
7136947 System and method for automatically synthesizing interfaces between incompatible protocols James A. Rowson, Alberto Sangiovanni-Vincentelli 2006-11-14