Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10713406 | Multi-die IC layout methods with awareness of mix and match die integration | Kwangsoo Han, Jiajia Li | 2020-07-14 |
| 9922161 | IC layout adjustment method and tool for improving dielectric reliability at interconnects | Tuck Boon Chan | 2018-03-20 |
| 9229686 | Accuracy configurable adders and methods | Seokhyeong Kang | 2016-01-05 |
| 9202003 | Gate-length biasing for digital circuit optimization | Puneet Gupta | 2015-12-01 |
| 9166567 | Data-retained power-gating circuit and devices including the same | Bong-il Park, Seok Hyeong KANG, Jae Gon Lee | 2015-10-20 |
| 9069926 | Standard cells having transistors annotated for gate-length biasing | Puneet Gupta | 2015-06-30 |
| 8949768 | Standard cells having transistors annotated for gate-length biasing | Puneet Gupta | 2015-02-03 |
| 8869094 | Standard cells having transistors annotated for gate-length biasing | Puneet Gupta | 2014-10-21 |
| 8756555 | Standard cells having transistors annotated for gate-length biasing | Puneet Gupta | 2014-06-17 |
| 8751974 | Layout decomposition for double patterning lithography | Hailong Yao | 2014-06-10 |
| 8635583 | Standard cells having transistors annotated for gate-length biasing | Puneet Gupta | 2014-01-21 |
| 8490043 | Standard cells having transistors annotated for gate-length biasing | Puneet Gupta | 2013-07-16 |
| 8402396 | Layout decomposition for double patterning lithography | Hailong Yao | 2013-03-19 |
| 8185865 | Methods for gate-length biasing using annotation data | Puneet Gupta | 2012-05-22 |
| 8127266 | Gate-length biasing for digital circuit optimization | Puneet Gupta | 2012-02-28 |
| 8103981 | Tool for modifying mask design layout | Puneet Gupta, Dennis Sylvester, Jie Yang | 2012-01-24 |
| 8073977 | Internet telephony through hosts | Jonathan Cox, Puneet Sharma | 2011-12-06 |
| 8024675 | Method and system for wafer topography-aware integrated circuit design analysis and optimization | Puneet Gupta, Puneet Sharma, Swamy Muddu | 2011-09-20 |
| 7945870 | Method and apparatus for detecting lithographic hotspots in a circuit layout | Chul-Hong Park, Xu Xu | 2011-05-17 |
| 7873929 | Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction | Chul-Hong Park | 2011-01-18 |
| 7865856 | System and method for performing transistor-level static performance analysis using cell-level static analysis tools | Puneet Gupta, Saumil Shah | 2011-01-04 |
| 7823098 | Method of designing a digital circuit by correlating different static timing analyzers | Cho Moon, Puneet Gupta, Paul J. Donehue | 2010-10-26 |
| 7814456 | Method and system for topography-aware reticle enhancement | Puneet Gupta | 2010-10-12 |
| 7745239 | Arrangement of fill unit elements in an integrated circuit interconnect layer | O. Samuel Nakagawa, Pakman Wong, Puneet Gupta | 2010-06-29 |
| 7743349 | Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit | Puneet Gupta | 2010-06-22 |