Cho Moon — 9 Patents at Synopsys

Cho Moon has been granted 9 US patents while listed as an inventor at Synopsys. The first was granted in 2005 and the most recent in December 2024. Cho Moon ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Cho Moon in San Diego, CA, US.

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12175181	Timing-aware surgical optimization for engineering change order in chip design	Bon Woong Ku, Nahmsuk Oh	2024-12-24	$178,045,000
8701074	Automatic reduction of modes of electronic circuits for timing analysis	Subramanyam Sripada	2014-04-15	$2,542,000
8627262	Automatic generation of merged mode constraints for electronic circuits	Subramanyam Sripada, Sonia Singhal	2014-01-07	$4,268,000
8607186	Automatic verification of merged mode constraints for electronic circuits	Subramanyam Sripada, Sonia Singhal	2013-12-10	$10,726,000
8261221	Comparing timing constraints of circuits	Sonia Singhal, Loa Mize	2012-09-04	$4,639,000
7823098	Method of designing a digital circuit by correlating different static timing analyzers	Puneet Gupta, Paul J. Donehue, Andrew B. Kahng	2010-10-26
7418684	Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks	Harish Kriplani	2008-08-26	$5,262,000
7356451	Assertion handling for timing model extraction	Harish Kriplani, Krishna Belkhale	2008-04-08	$7,428,000
6928630	Timing model extraction by timing graph reduction	Harish Kriplani, Krishna Belkhale	2005-08-09	$7,870,000

Cho Moon — 9 Patents

Issued Patents All Time

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