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USPTO Patent Rankings Data through Dec 31, 2025
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Nahmsuk Oh — 15 Patents

SYSynopsys: 15 patents #39 of 2,302Top 2%
Palo Alto, CA: #1,617 of 9,675 inventorsTop 20%
California: #40,789 of 386,348 inventorsTop 15%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Nahmsuk Oh has been granted 15 US patents while listed as an inventor at Synopsys. The first was granted in 2008 and the most recent in December 2024. Nahmsuk Oh ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Nahmsuk Oh in Palo Alto, CA, US.

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12175181 Timing-aware surgical optimization for engineering change order in chip design Bon Woong Ku, Cho Moon 2024-12-24 $178,045,000
11537775 Timing and placement co-optimization for engineering change order (ECO) cells 2022-12-27 $322,229,000
10867091 Machine learning based power optimization using parallel training and localized data generation Antun Domic 2020-12-15 $38,696,000
10817634 Machine-learning circuit optimization using quantized prediction functions 2020-10-27 $39,221,000
10339258 Look-ahead timing prediction for multi-instance module (MIM) engineering change order (ECO) Seungwhun Paik, Subramanyam Sripada, Rupesh Nayak 2019-07-02 $21,466,000
9390221 Linear complexity prioritization of timing engineering change order failures Seungwhun Paik, Jia-Yin Wang 2016-07-12 $7,647,000
8924906 Determining a design attribute by estimation and by calibration of estimated value Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada 2014-12-30 $4,224,000
8555235 Determining a design attribute by estimation and by calibration of estimated value Peivand Fallah-Tehrani, Alireza Kasnavl, Subramanyam Sripada 2013-10-08 $4,440,000
8407655 Fixing design requirement violations in multiple multi-corner multi-mode scenarios Rupesh Nayak, William Chiu-Ting Shu 2013-03-26 $3,032,000
8341574 Crosstalk time-delay analysis using random variables Ravikishore Gandikota, Li Ding, Peivand Tehrani, Alireza Kasnavi 2012-12-25
8336013 Determining an order for visiting circuit blocks in a circuit design for fixing design requirement violations Peivand Tehrani, William Chiu-Ting Shu 2012-12-18 $8,212,000
8219952 Variation aware victim and aggressor timing overlap detection by pessimism reduction based on relative positions of timing windows Peivand Tehrani, Christopher Papademetrious 2012-07-10 $3,650,000
7962876 Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques Peivand Fallah-Tehrani, Alireza Kasnavi 2011-06-14 $2,204,000
7900165 Determining a design attribute by estimation and by calibration of estimated value Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada 2011-03-01 $2,192,000
7454731 Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques Peivand Fallah-Tehrani, Alireza Kasnavi 2008-11-18 $3,128,000