| 12406127 |
Static timing analysis of multi-die three-dimensional integrated circuits |
Song Chen |
2025-09-02 |
| 10339258 |
Look-ahead timing prediction for multi-instance module (MIM) engineering change order (ECO) |
Seungwhun Paik, Nahmsuk Oh, Rupesh Nayak |
2019-07-02 |
| 9489478 |
Simplifying modes of an electronic circuit by reducing constraints |
Ajit Sequeira, Subrahmanya Narasimha Murthy Palla |
2016-11-08 |
| 8924906 |
Determining a design attribute by estimation and by calibration of estimated value |
Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi |
2014-12-30 |
| 8701074 |
Automatic reduction of modes of electronic circuits for timing analysis |
Cho Moon |
2014-04-15 |
| 8627262 |
Automatic generation of merged mode constraints for electronic circuits |
Sonia Singhal, Cho Moon |
2014-01-07 |
| 8607186 |
Automatic verification of merged mode constraints for electronic circuits |
Sonia Singhal, Cho Moon |
2013-12-10 |
| 8555235 |
Determining a design attribute by estimation and by calibration of estimated value |
Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavl |
2013-10-08 |
| 8473886 |
Parallel parasitic processing in static timing analysis |
Qiuyang Wu, Patrick D. Fortner |
2013-06-25 |
| 7900165 |
Determining a design attribute by estimation and by calibration of estimated value |
Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi |
2011-03-01 |
| 7739098 |
System and method for providing distributed static timing analysis with merged results |
Kayhan Kucukcakar, Steve Hollands, Brian Clerkin, Loa Mize, Qiuyang Wu +1 more |
2010-06-15 |
| 7523428 |
Hierarchical signal integrity analysis using interface logic models |
— |
2009-04-21 |
| 7216317 |
Hierarchical signal integrity analysis using interface logic models |
— |
2007-05-08 |