Subramanyam Sripada — 14 Patents at Synopsys

Subramanyam Sripada has been granted 14 US patents while listed as an inventor at Synopsys. The first was granted in 2007 and the most recent in December 2025. Subramanyam Sripada ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Subramanyam Sripada in Portland, OR, US.

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12488169	Performing timing constraint equivalence checking on circuit designs	Gowrishankar N. J., Shubhashish Rudra, Ajit Sequeira	2025-12-02
12406127	Static timing analysis of multi-die three-dimensional integrated circuits	Song Chen	2025-09-02
10339258	Look-ahead timing prediction for multi-instance module (MIM) engineering change order (ECO)	Seungwhun Paik, Nahmsuk Oh, Rupesh Nayak	2019-07-02	$21,466,000
9489478	Simplifying modes of an electronic circuit by reducing constraints	Ajit Sequeira, Subrahmanya Narasimha Murthy Palla	2016-11-08	$14,717,000
8924906	Determining a design attribute by estimation and by calibration of estimated value	Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi	2014-12-30	$4,224,000
8701074	Automatic reduction of modes of electronic circuits for timing analysis	Cho Moon	2014-04-15	$2,542,000
8627262	Automatic generation of merged mode constraints for electronic circuits	Sonia Singhal, Cho Moon	2014-01-07	$4,268,000
8607186	Automatic verification of merged mode constraints for electronic circuits	Sonia Singhal, Cho Moon	2013-12-10	$10,726,000
8555235	Determining a design attribute by estimation and by calibration of estimated value	Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavl	2013-10-08	$4,440,000
8473886	Parallel parasitic processing in static timing analysis	Qiuyang Wu, Patrick D. Fortner	2013-06-25	$3,652,000
7900165	Determining a design attribute by estimation and by calibration of estimated value	Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi	2011-03-01	$2,192,000
7739098	System and method for providing distributed static timing analysis with merged results	Kayhan Kucukcakar, Steve Hollands, Brian Clerkin, Loa Mize, Qiuyang Wu +1 more	2010-06-15	$2,189,000
7523428	Hierarchical signal integrity analysis using interface logic models	—	2009-04-21	$4,880,000
7216317	Hierarchical signal integrity analysis using interface logic models	—	2007-05-08	$9,889,000

Subramanyam Sripada — 14 Patents

Issued Patents All Time

Patent Widget