Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7730432 | Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objective | Puneet Gupta, Dave Reed | 2010-06-01 |
| 7716612 | Method and system for integrated circuit optimization by using an optimized standard-cell library | Puneet Gupta, Saumil Shah | 2010-05-11 |
| 7676772 | Layout description having enhanced fill annotation | O. Samuel Nakagawa, Pakman Wong | 2010-03-09 |
| 7640522 | Method and system for placing layout objects in a standard-cell layout | Puneet Gupta, Chul-Hong Park | 2009-12-29 |
| 7627849 | System and method for varying the starting conditions for a resolution enhancement program to improve the probability that design goals will be met | Puneet Gupta | 2009-12-01 |
| 7614032 | Method for correcting a mask design layout | Puneet Gupta, Dennis Sylvester, Jie Yang | 2009-11-03 |
| 7441211 | Gate-length biasing for digital circuit optimization | Puneet Gupta | 2008-10-21 |
| 7149999 | Method for correcting a mask design layout | Puneet Gupta, Dennis Sylvester, Jie Yang | 2006-12-12 |
| 7062743 | Floorplan evaluation, global routing, and buffer insertion for integrated circuits | Christoph Albrecht, Ion Mandoiu, Alexander Z. Zelikovsky | 2006-06-13 |
| 6047117 | Diffusion-based method and apparatus for determining circuit interconnect voltage response | Sudhakar Muddu | 2000-04-04 |