Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11861281 | Computer-implemented method and computing system for designing integrated circuit by considering timing delay | Jong Pil Lee, Moon-su Kim, Sun-ik Heo | 2024-01-02 |
| 11475195 | Computer-implemented method and computing system for designing integrated circuit by considering timing delay | Jong Pil Lee, Moon-su Kim, Sun-ik Heo | 2022-10-18 |
| 10902168 | Computer-implemented method and computing system for designing integrated circuit by considering timing delay | Jong Pil Lee, Moon-su Kim, Sun-ik Heo | 2021-01-26 |
| 10432183 | Clock generation circuit having deskew function and semiconductor integrated circuit device including same | Jin Song, Jae Gon Lee | 2019-10-01 |
| 10096302 | Display system | Jong Ho Roh | 2018-10-09 |
| 9268395 | Hierarchical power management circuit, power management method using the same, and system on chip including the hierarchical power management circuit | Jae Gon Lee, Moo Kyung Kang | 2016-02-23 |
| 9166567 | Data-retained power-gating circuit and devices including the same | Andrew B. Kahng, Seok Hyeong KANG, Jae Gon Lee | 2015-10-20 |
| 8726047 | System on chip, devices having the same, and method for power control of the SOC | Jae Gon Lee, Jang-Ho Cho, Kwang Ho Kim, Taek Kyun Shin, Dong Keun Kim +2 more | 2014-05-13 |
| 8013627 | Semiconductor device and method of fabricating the same | — | 2011-09-06 |
| 7415685 | Method of verifying the power off effect of a design entity at register transfer level and method of modeling the power off effect | Jeong Joo LEE | 2008-08-19 |