Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11755799 | Diversifying stimulus generation in constrained random simulation by learning distribution history | — | 2023-09-12 |
| 9721057 | System and method for netlist clock domain crossing verification | Mohamed Shaker Sarwary, Maher Mneimneh, Paras Mal Jain, Mohammad H. Movahed-Ezazi, Pronay Kumar Biswas +1 more | 2017-08-01 |
| 8707272 | Scenario driven concurrency bugs: model and check | — | 2014-04-22 |
| 8589126 | System and method for model checking by interleaving stateless and state-based methods | Chao Wang, Weihong Li | 2013-11-19 |
| 8538900 | Integrating interval constraint propagation with nonlinear real arithmetic | Sicun Gao, Franjo Ivancic, Aarti Gupta | 2013-09-17 |
| 8539013 | Efficient decision method for real non-linear arithmetic constraints | Franjo Ivancic | 2013-09-17 |
| 8539451 | Systems and methods for model checking the precision of programs employing floating-point operations | Franjo Ivancic, Sriram Sankaranarayanan, Aarti Gupta | 2013-09-17 |
| 8532971 | DPLL-based SAT solver using with application-aware branching | — | 2013-09-10 |
| 8504330 | Parallelizing bounded model checking using tunnels over a distributed framework | — | 2013-08-06 |
| 8448145 | Methods and systems for reducing verification conditions for concurrent programs using mutually atomic transactions | Sudipta Kundu | 2013-05-21 |
| 8131532 | Software verification using range analysis | Srihari Cadambi, Aleksandr Zaks, Franjo Ivancic, Ilya SHLYAKHTER, Zijiang Yang +2 more | 2012-03-06 |
| 8131661 | Efficient decision procedure for bounded integer non-linear operations using SMT(LIA) | — | 2012-03-06 |
| 8005661 | Modeling and verification of concurrent systems using SMT-based BMC | Aarti Gupta | 2011-08-23 |
| 7949511 | System and method for tunneling and slicing based BMC decomposition | — | 2011-05-24 |
| 7930659 | Software verification | Franjo Ivancic, Aarti Gupta, Himanshu Jain | 2011-04-19 |
| 7853906 | Accelerating high-level bounded model checking | Aarti Gupta | 2010-12-14 |
| 7742907 | Iterative abstraction using SAT-based BMC with proof analysis | Aarti Gupta, Zijiang Yang, Pranav Ashar | 2010-06-22 |
| 7743352 | Computer implemented method of high-level synthesis for the efficient verification of computer software | Aarti Gupta | 2010-06-22 |
| 7711525 | Efficient approaches for bounded model checking | Lintao Zhang, Aarti Gupta, Zijiang Yang, Pranav Ashar | 2010-05-04 |
| 7386818 | Efficient modeling of embedded memories in bounded memory checking | Aarti Gupta, Pranav Ashar | 2008-06-10 |
| 7346486 | System and method for modeling, abstraction, and analysis of software | Franjo Ivancic, Pranav Ashar, Aarti Gupta, Zijiang Yang | 2008-03-18 |
| 7305637 | Efficient SAT-based unbounded symbolic model checking | Aarti Gupta, Pranav Ashar | 2007-12-04 |
| 7203917 | Efficient distributed SAT and SAT-based distributed bounded model checking | Aarti Gupta, Zijiang Yang, Pranav Ashar | 2007-04-10 |
| 6473884 | Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis | Geert Janssen, Florian Krohm, Andreas Kuehlmann, Viresh Paruthi | 2002-10-29 |