Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10690722 | Methods and systems for efficient identification of glitch failures in integrated circuits | Fabrice Baray, Hari Mony, Nikhil Rahagude, Vikas Sachdeva | 2020-06-23 |
| 9965575 | Methods and systems for correcting X-pessimism in gate-level simulation or emulation | Ian Andrew Guyler, Sanjeev Mahajan | 2018-05-08 |
| 8131532 | Software verification using range analysis | Srihari Cadambi, Aleksandr Zaks, Franjo Ivancic, Ilya SHLYAKHTER, Zijiang Yang +2 more | 2012-03-06 |
| 7742907 | Iterative abstraction using SAT-based BMC with proof analysis | Aarti Gupta, Malay Ganai, Zijiang Yang | 2010-06-22 |
| 7711525 | Efficient approaches for bounded model checking | Malay Ganai, Lintao Zhang, Aarti Gupta, Zijiang Yang | 2010-05-04 |
| 7386818 | Efficient modeling of embedded memories in bounded memory checking | Malay Ganai, Aarti Gupta | 2008-06-10 |
| 7383166 | Verification of scheduling in the presence of loops using uninterpreted symbolic simulation | Anand Raghunathan, Subhrajit Bhattacharya | 2008-06-03 |
| 7346486 | System and method for modeling, abstraction, and analysis of software | Franjo Ivancic, Malay Ganai, Aarti Gupta, Zijiang Yang | 2008-03-18 |
| 7305637 | Efficient SAT-based unbounded symbolic model checking | Malay Ganai, Aarti Gupta | 2007-12-04 |
| 7203917 | Efficient distributed SAT and SAT-based distributed bounded model checking | Malay Ganai, Aarti Gupta, Zijiang Yang | 2007-04-10 |
| 7019674 | Content-based information retrieval architecture | Srihari Cadambi, Joseph Kilian, Srimat Chakradhar | 2006-03-28 |
| 6975976 | Property specific testbench generation framework for circuit design validation by guided simulation | Albert E. Casavant, Aarti Gupta | 2005-12-13 |
| 6874135 | Method for design validation using retiming | Aarti Gupta, Sharad Malik | 2005-03-29 |
| 6816827 | Verification method for combinational loop systems | Yang Xia | 2004-11-09 |
| 6816825 | Simulation vector generation from HDL descriptions for observability-enhanced statement coverage | Srinivas Devadas, Farzan Fallah | 2004-11-09 |
| 6745160 | Verification of scheduling in the presence of loops using uninterpreted symbolic simulation | Anand Raghunathan, Subhrajit Bhattacharya, Aarti Gupta | 2004-06-01 |
| 6728665 | SAT-based image computation with application in reachability analysis | Aarti Gupta, Zijiang Yang | 2004-04-27 |
| 6662323 | Fast error diagnosis for combinational verification | Aarti Gupta | 2003-12-09 |
| 6651234 | Partition-based decision heuristics for SAT and image computation using SAT and BDDs | Aarti Gupta, Zijiang Yang, Sharad Malik | 2003-11-18 |
| 6496961 | Dynamic detection and removal of inactive clauses in SAT with application in image computation | Aarti Gupta, Zijiang Yang, Anubhav Gupta | 2002-12-17 |
| 6415430 | Method and apparatus for SAT solver architecture with very low synthesis and layout overhead | Peixin Zhong, Margaret Martonosi | 2002-07-02 |
| 6324673 | Method and apparatus for edge-endpoint-based VLSI design rule checking | Zhen Luo, Margaret Martonosi | 2001-11-27 |
| 6247164 | Configurable hardware system implementing Boolean Satisfiability and method thereof | Sharad Malik, Margaret Martonosi, Peixin Zhong | 2001-06-12 |
| 6223141 | Speeding up levelized compiled code simulation using netlist transformations | — | 2001-04-24 |
| 6163876 | Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow | Subhrajit Bhattacharya, Anand Raghunathan, Akira MUKAIYAMA | 2000-12-19 |