Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9965575 | Methods and systems for correcting X-pessimism in gate-level simulation or emulation | Pranav Ashar, Sanjeev Mahajan | 2018-05-08 |
| 7168059 | Graphical loop profile analysis | Bryan Darrell Bowyer, David Gaines Burnette | 2007-01-23 |
| 6917909 | Facilitating guidance provision for an architectural exploration based design creation process | Lev Markov, Shiv Prakash, David Gaines Burnette | 2005-07-12 |