Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515168 | Formal verification using microtransactions | Pankaj P. Chauhan, Sameer Kapoor, Saurabh Jain, Kunal Bindal, Andres R. Takach +3 more | 2019-12-24 |
| 9817929 | Formal verification using microtransactions | Pankaj P. Chauhan, Sameer Kapoor, Saurabh Jain, Kunal Bindal, Andres R. Takach +3 more | 2017-11-14 |
| 8522197 | Hierarchical presentation techniques for a design tool | Peter Pius Gutberlet, Simon Joshua Waters | 2013-08-27 |
| 8219949 | Nonsequential hardware design synthesis verification | Robert J. Condon, Andres R. Takach | 2012-07-10 |
| 7844944 | Hierarchical presentation techniques for a design tool | Peter Pius Gutberlet, Simon Joshua Waters | 2010-11-30 |
| 7831938 | Interactive interface resource allocation in a behavioral synthesis tool | Peter Pius Gutberlet, Simon Joshua Waters | 2010-11-09 |
| 7712050 | Hierarchical presentation techniques for a design tool | Peter Pius Gutberlet, Simon Joshua Waters | 2010-05-04 |
| 7412684 | Loop manipulation in a behavioral synthesis tool | Peter Pius Gutberlet, Andres R. Takach | 2008-08-12 |
| 7310787 | Array transformation in a behavioral synthesis tool | Shiv Prakash, Peter Pius Gutberlet | 2007-12-18 |
| 7302670 | Interactive interface resource allocation in a behavioral synthesis tool | Peter Pius Gutberlet, Simon Joshua Waters | 2007-11-27 |
| 7168059 | Graphical loop profile analysis | David Gaines Burnette, Ian Andrew Guyler | 2007-01-23 |
| 7120879 | Hierarchical presentation techniques for a design tool | Peter Pius Gutberlet, Simon Joshua Waters | 2006-10-10 |