MM

Margaret Martonosi

PU Princeton University: 6 patents #94 of 1,197Top 8%
NE Nec: 4 patents #14 of 91Top 20%
AS Agere Systems: 1 patents #984 of 1,849Top 55%
📍 Skillman, NJ: #53 of 228 inventorsTop 25%
🗺 New Jersey: #11,005 of 69,400 inventorsTop 20%
Overall (All Time): #646,807 of 4,157,543Top 20%
8
Patents All Time

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDate
9524232 Inter-core cooperative TLB prefetchers Abhishek Bhattacharjee 2016-12-20
8880844 Inter-core cooperative TLB prefetchers Abhishek Bhattacharjee 2014-11-04
7472302 Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay Zhigang Hu, Stefanos Kaxiras 2008-12-30
6745336 System and method of operand value based processor optimization by detecting a condition of pre-determined number of bits and selectively disabling pre-determined bit-fields by clock gating David R. Brooks 2004-06-01
6415430 Method and apparatus for SAT solver architecture with very low synthesis and layout overhead Pranav Ashar, Peixin Zhong 2002-07-02
6324673 Method and apparatus for edge-endpoint-based VLSI design rule checking Zhen Luo, Pranav Ashar 2001-11-27
6247164 Configurable hardware system implementing Boolean Satisfiability and method thereof Pranav Ashar, Sharad Malik, Peixin Zhong 2001-06-12
6038392 Implementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardware Pranav Ashar, Sharad Malik, Peixin Zhong 2000-03-14