Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12001845 | Decoupled access-execute processing | Mbou Eyole | 2024-06-04 |
| 11899940 | Apparatus and method for handling memory load requests | Mbou Eyole | 2024-02-13 |
| 11886881 | Decoupled access-execute processing and prefetching control | Mbou Eyole, Michiel Willem Van Tol | 2024-01-30 |
| 11334485 | System and method for dynamic enforcement of store atomicity | Alberto Ros | 2022-05-17 |
| 11237966 | System and method for event monitoring in cache coherence protocols without explicit invalidations | Alberto Ros | 2022-02-01 |
| 11188464 | System and method for self-invalidation, self-downgrade cachecoherence protocols | Alberto Ros | 2021-11-30 |
| 11163576 | Systems and methods for invisible speculative execution | Christos SAKALIS, Alberto Ros, Alexandra Jimborean, Magnus Själander | 2021-11-02 |
| 11119920 | Systems and methods for non-speculative store coalescing and generating atomic write sets using address subsets | Alberto Ros | 2021-09-14 |
| 11106468 | System and method for non-speculative reordering of load accesses | Alberto Ros | 2021-08-31 |
| 11068410 | Multi-core computer systems with private/shared cache line indicators | Alberto Ros | 2021-07-20 |
| 10915466 | System protecting caches from side-channel attacks | Erik E. Hagersten, David Black-Schaffer | 2021-02-09 |
| 10671543 | Systems and methods for reducing first level cache energy by eliminating cache address tags | Erik E. Hagersten, Andreas Sembrant, David Black-Schaffer | 2020-06-02 |
| 10528471 | System and method for self-invalidation, self-downgrade cachecoherence protocols | Alberto Ros | 2020-01-07 |
| 10402344 | Systems and methods for direct data access in multi-level cache memory hierarchies | Erik E. Hagersten, Andreas Sembrant, David Black-Schaffer | 2019-09-03 |
| 10402331 | Systems and methods for implementing a tag-less shared cache and a larger backing cache | Erik E. Hagersten, Andreas Sembrant, David Black-Schaffer | 2019-09-03 |
| 10387312 | System and method for event monitoring in cache coherence protocols without explicit invalidations | Alberto Ros | 2019-08-20 |
| 10324861 | Systems and methods for coherence in clustered cache hierarchies | Alberto Ros | 2019-06-18 |
| 9274960 | System and method for simplifying cache coherence using multiple write policies | Alberto Ros | 2016-03-01 |
| 7573880 | Set-associative memory architecture for routing tables | Georgios Keramidas | 2009-08-11 |
| 7472302 | Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay | Zhigang Hu, Margaret Martonosi | 2008-12-30 |
| 7096343 | Method and apparatus for splitting packets in multithreaded VLIW processor | Alan D. Berenbaum, Nevin C. Heintze, Tor E. Jeremiassen | 2006-08-22 |
| 7007153 | Method and apparatus for allocating functional units in a multithreaded VLIW processor | Alan D. Berenbaum, Nevin C. Heintze, Tor E. Jeremiassen | 2006-02-28 |
| 6983388 | Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines | Philip W. Diodato, Hubert Rae McLellan, Jr., Girija Narlikar | 2006-01-03 |
| 6889293 | Directory-based prediction methods and apparatus for shared-memory multiprocessor systems | Reginald Clifford Young | 2005-05-03 |
| 6665791 | Method and apparatus for releasing functional units in a multithreaded VLIW processor | Alan D. Berenbaum, Nevin C. Heintze, Tor E. Jeremiassen | 2003-12-16 |