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Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines |
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Inter-wiring-layer capacitors |
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| 6559499 |
Process for fabricating an integrated circuit device having capacitors with a multilevel metallization |
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Circuitry for delivering a signal to different load elements located in an electronic system |
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Digital logic circuits for frequency multiplication |
— |
1991-11-05 |