RL

Ruichen Liu

AT AT&T: 12 patents #1,455 of 18,772Top 8%
MC Macronix International Co.: 9 patents #200 of 1,241Top 20%
AS Agere Systems: 2 patents #639 of 1,849Top 35%
Overall (All Time): #185,910 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7880115 Method for laser annealing to form an epitaxial growth layer Sheng-Chih Lai 2011-02-01
7683360 Horizontal chalcogenide element defined by a pad for use in solid-state memories Yi-Chou Chen, Hsiang-Lan Lung 2010-03-23
7371604 Method of forming a contact structure Ming-Hsiu Lee 2008-05-13
7257018 Method and apparatus for a low write current MRAM having a write magnet ChiaHua Ho, Yi-Chou Chen 2007-08-14
7247503 Method of laser annealing to form an epitaxial growth layer Sheng-Chih Lai 2007-07-24
7135727 I-shaped and L-shaped contact structures and their fabrication methods Ming-Hsiu Lee 2006-11-14
7038230 Horizontal chalcogenide element defined by a pad for use in solid-state memories Yi-Chou Chen, Hsiang-Lan Lung 2006-05-02
6965522 Tunneling diode magnetic junction memory Hsiang-Lan Lung 2005-11-15
6927136 Non-volatile memory cell having metal nano-particles for trapping charges and fabrication thereof Hsiang-Lan Lung, Kuang Yeu Hsieh, Tai-Bor Wu, Jiun-Yi Tseng 2005-08-09
6794694 Inter-wiring-layer capacitors Philip W. Diodato, Chun-Ting Liu 2004-09-21
6559499 Process for fabricating an integrated circuit device having capacitors with a multilevel metallization Glenn B. Alers, Philip W. Diodato 2003-05-06
6149778 Article comprising fluorinated amorphous carbon and method for fabricating article Sungho Jin, Chien-Shing Pai, Wei Zhu 2000-11-21
6147407 Article comprising fluorinated amorphous carbon and process for fabricating article Sungho Jin, Chien-Shing Pai, Wei Zhu 2000-11-14
6110831 Method of mechanical polishing James T. Cargo, Ronald J. Holmes, Alvaro Maury 2000-08-29
5956618 Process for producing multi-level metallization in an integrated circuit Chun-Ting Liu, Kuo-Hua Lee 1999-09-21
5438006 Method of fabricating gate stack having a reduced height Chorng-Ping Chang, Kuo-Hua Lee, Chun-Ting Liu 1995-08-01
5420058 Method of making field effect transistor with a sealed diffusion junction Kuo-Hua Lee, Chun-Ting Liu 1995-05-30
5407859 Field effect transistor with landing pad Kuo-Hua Lee, Chun-Ting Liu 1995-04-18
5395787 Method of manufacturing shallow junction field effect transistor Kuo-Hua Lee, Chun-Ting Liu 1995-03-07
5063422 Devices having shallow junctions Steven J. Hillenius, Joseph Lebowitz, William T. Lynch 1991-11-05
5008217 Process for fabricating integrated circuits having shallow junctions Christopher J. Case, Kin P. Cheung, Ronald J. Schutz, Richard S. Wagner, II 1991-04-16
4914500 Method for fabricating semiconductor devices which include sources and drains having metal-containing material regions, and the resulting devices William T. Lynch, David S. Williams 1990-04-03
4588928 Electron emission system Michael G. R. Thomson 1986-05-13