Issued Patents All Time
Showing 1–25 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12419054 | Three-dimensional memory array with local line selector | Chen-Jun Wu, Yu-Wei Jiang | 2025-09-16 |
| 12414295 | Semiconductor memory structure and method for forming the same | Yu-Wei Jiang, Hung-Chang Sun, Kuo-Chang Chiang, TsuChing Yang | 2025-09-09 |
| 12406708 | Memory device with unipolar selector | — | 2025-09-02 |
| 12389607 | Bipolar selector with independently tunable threshold voltages | Chung-Te Lin, Min Cao, Randy B. Osborne | 2025-08-12 |
| 12382639 | Three-dimensional memory device and method | TsuChing Yang, Hung-Chang Sun, Kuo-Chang Chiang, Yu-Wei Jiang | 2025-08-05 |
| 12376310 | Memory cell having source or drain electrode with kink portion, memory array and manufacturing method thereof | Yu-Wei Jiang, TsuChing Yang, Feng-Cheng Yang, Chung-Te Lin | 2025-07-29 |
| 12363907 | Memory device comprising conductive pillars | Yu-Wei Jiang, TsuChing Yang, Hung-Chang Sun, Kuo-Chang Chiang | 2025-07-15 |
| 12363911 | Semiconductor structure and method for forming thereof | Yu-Wei Jiang, Feng-Cheng Yang, Chung-Te Lin | 2025-07-15 |
| 12356628 | Memory device and method for making same | Yu-Wei Jiang, Hung-Chang Sun, Kuo-Chang Chiang, TsuChing Yang | 2025-07-08 |
| 12354634 | Transistorless memory cell | Katherine H. Chiang, Chung-Te Lin, Min Cao, Yuh-Jier Mii | 2025-07-08 |
| 12349362 | High selectivity isolation structure for improving effectiveness of 3D memory fabrication | Tsu Ching Yang, Feng-Cheng Yang, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun +2 more | 2025-07-01 |
| 12342539 | Protective liner layers in 3D memory structure | Tsu Ching Yang, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu +2 more | 2025-06-24 |
| 12336183 | Three-dimensional ferroelectric random access memory devices and methods of forming | TsuChing Yang, Hung-Chang Sun, Kuo-Chang Chiang, Yu-Wei Jiang | 2025-06-17 |
| 12336180 | Memory cell array with increased source bias voltage | Chen-Jun Wu, Sun Yi Chang, Chung-Te Lin | 2025-06-17 |
| 12317541 | Semiconductor device and manufacturing method thereof | Yu-Wei Jiang, Feng-Cheng Yang, Chung-Te Lin | 2025-05-27 |
| 12302583 | 3D ferroelectric memory | Chung-Te Lin | 2025-05-13 |
| 12302562 | Semiconductor structure and method of forming the same | Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, TsuChing Yang, Feng-Cheng Yang +1 more | 2025-05-13 |
| 12288820 | Transistor, integrated circuit, and manufacturing method of transistor | Hung-Chang Sun, Yu-Wei Jiang, Kuo-Chang Chiang, TsuChing Yang, Feng-Cheng Yang +1 more | 2025-04-29 |
| 12272750 | Memory array channel regions | Kuo-Chang Chiang, Hung-Chang Sun, TsuChing Yang, Yu-Wei Jiang | 2025-04-08 |
| 12266408 | Vertical fuse memory in one-time program memory cells | Chung-Te Lin | 2025-04-01 |
| 12268005 | Semiconductor structure | Chung-Te Lin | 2025-04-01 |
| 12219777 | Memory array source/drain electrode structures | Kuo-Chang Chiang, Hung-Chang Sun, TsuChing Yang, Yu-Wei Jiang | 2025-02-04 |
| 12219880 | Integrated circuit device | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2025-02-04 |
| 12218250 | Oxide semiconductor transistor structure in 3-d device and methods for forming the same | Kuo-Chang Chiang, Hung-Chang Sun, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang +1 more | 2025-02-04 |
| 12185531 | 3D NOR type memory array with wider source/drain conductive lines | Yu-Wei Jiang, Feng-Cheng Yang, Chung-Te Lin | 2024-12-31 |