Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12419054 | Three-dimensional memory array with local line selector | Yu-Wei Jiang, Sheng-Chih Lai | 2025-09-16 |
| 12349362 | High selectivity isolation structure for improving effectiveness of 3D memory fabrication | Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang +2 more | 2025-07-01 |
| 12342539 | Protective liner layers in 3D memory structure | Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun +2 more | 2025-06-24 |
| 12336180 | Memory cell array with increased source bias voltage | Sun Yi Chang, Sheng-Chih Lai, Chung-Te Lin | 2025-06-17 |
| 12176022 | Programming and reading circuit for dynamic random access memory | Yun-Feng Kao, Sheng-Chih Lai, Katherine H. Chiang, Chung-Te Lin | 2024-12-24 |
| 12048164 | Memory array and operation method thereof | Wen-Ling Lu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin +2 more | 2024-07-23 |
| 12035534 | Three-dimensional memory array with local line selector | Yu-Wei Jiang, Sheng-Chih Lai | 2024-07-09 |
| 11723199 | Protective liner layers in 3D memory structure | Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun +2 more | 2023-08-08 |
| 11723210 | High selectivity isolation structure for improving effectiveness of 3D memory fabrication | Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang +2 more | 2023-08-08 |
| 11672123 | Three-dimensional memory array with local line selector | Yu-Wei Jiang, Sheng-Chih Lai | 2023-06-06 |
| 10381094 | 3D memory with staged-level multibit programming | Chih-Chang Hsieh, Tzu-Hsuan Hsu, Hang-Ting Lue | 2019-08-13 |
| 9263143 | Three dimensional memory device and data erase method thereof | Tzu-Hsuan Hsu, Hang-Ting Lue | 2016-02-16 |