Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10803412 | Scheduling crop transplantations | Sambuddha Roy, Yogish Sabharwal, Jayasuriya M. R. Sarath Bandara, Vanessa Teo | 2020-10-13 |
| 10049456 | Verification of business processes using spatio-temporal data | Nilanjan Banerjee, Umamaheswari C. Devi, Raghavendra Singh | 2018-08-14 |
| 7870531 | System for using partitioned masks to build a chip | John Darringer, Daniel L. Ostapko | 2011-01-11 |
| 7516424 | Modeling and simulating a powergated hierarchical element | Stephen John Barnfield, Daniel R. Knebel, Stephen V. Kosonocky | 2009-04-07 |
| 7500207 | Influence-based circuit design | Anthony Correale, Jr., Nathaniel D. Hieter, Veena S. Pureswaran, Ruchir Puri | 2009-03-03 |
| 7479801 | Power gating techniques able to have data retention and variability immunity properties | — | 2009-01-20 |
| 7469401 | Method for using partitioned masks to build a chip | John Darringer, Daniel L. Ostapko | 2008-12-23 |
| 7420388 | Power gating techniques able to have data retention and variability immunity properties | — | 2008-09-02 |
| 7383166 | Verification of scheduling in the presence of loops using uninterpreted symbolic simulation | Pranav Ashar, Anand Raghunathan | 2008-06-03 |
| 7126370 | Power gating techniques able to have data retention and variability immunity properties | — | 2006-10-24 |
| 6993740 | Methods and arrangements for automatically interconnecting cores in systems-on-chip | Reinaldo A. Bergamaschi | 2006-01-31 |
| 6745160 | Verification of scheduling in the presence of loops using uninterpreted symbolic simulation | Pranav Ashar, Anand Raghunathan, Aarti Gupta | 2004-06-01 |
| 6477691 | Methods and arrangements for automatic synthesis of systems-on-chip | Reinaldo A. Bergamashi/Rab, Jean-Marc Daveau, William Lee | 2002-11-05 |
| 6163876 | Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow | Pranav Ashar, Anand Raghunathan, Akira MUKAIYAMA | 2000-12-19 |
| 5748647 | Low cost testing method for register transfer level circuits | Sujit Dey | 1998-05-05 |