Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7870531 | System for using partitioned masks to build a chip | Subhrajit Bhattacharya, John Darringer | 2011-01-11 |
| 7469401 | Method for using partitioned masks to build a chip | Subhrajit Bhattacharya, John Darringer | 2008-12-23 |
| 7302671 | Integrated circuit logic with self compensating shapes | Fook-Luen Heng, Jin-Fuw Lee | 2007-11-27 |
| 7269817 | Lithographic process window optimization under complex constraints on edge placement | Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Alan E. Rosenbluth, Nakgeuon Seong | 2007-09-11 |
| 7084476 | Integrated circuit logic with self compensating block delays | Puneet Gupta, Fook-Luen Heng, David S. Kung | 2006-08-01 |
| 6430731 | Methods and apparatus for performing slew dependent signal bounding for signal timing analysis | Jin-Fuw Lee, Jeffrey P. Soreff, Chak-Kuen Wong | 2002-08-06 |
| 6383847 | Partitioned mask layout | Gary S. Ditlow, Fook-Luen Heng, Mark A. Lavin, Jung Hyuk YOON | 2002-05-07 |
| 6144224 | Clock distribution network with dual wire routing | Jin-Fuw Lee | 2000-11-07 |
| 5994924 | Clock distribution network with dual wire routing | Jin-Fuw Lee | 1999-11-30 |
| 4559611 | Mapping and memory hardware for writing horizontal and vertical lines | — | 1985-12-17 |