SD

Sujit Dey

NE Nec: 10 patents #7,889 of 14,502Top 55%
University of California: 7 patents #1,047 of 18,278Top 6%
AC Allot Communications: 2 patents #4 of 36Top 15%
NI Nec Research Institute: 1 patents #57 of 127Top 45%
PU Princeton University: 1 patents #543 of 1,197Top 50%
Overall (All Time): #223,468 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9756142 System and method for delivering video data from a server in a wireless network by caching the video data Hasti Ahlehagh 2017-09-05
9113176 Network and device aware video scaling system, method, software, and device Naomi Ramos 2015-08-18
8606966 Network adaptation of digital content Debashis Panigrahi, Douglas Wong, Parag Arole 2013-12-10
8351513 Intelligent video signal encoding utilizing regions of interest information Jiangtao Gene Wen, Parag Arole, Jinwen Zan, Supriya Bhat, Andjela Illic 2013-01-08
8060807 Content and channel aware object scheduling and error control Debashis Panigrahi 2011-11-15
8010655 Network monitoring system and method Nishant Mittal, Debashis Panigrahi 2011-08-30
7808941 Dynamic adaptation for wireless communications with enhanced quality of service Naomi Ramos, Debashis Panigrahi 2010-10-05
7793188 Apparatus and method for improving reliability of collected sensor data over a network Shoubhik Mukhopadhyay, Debashis Panigrahi 2010-09-07
7743161 Digital content buffer for adaptive streaming Douglas Wong, Jiangtao Gene Wen, Yusuke Takebuchi, Parag Arole, Debashi Panigrahi 2010-06-22
6978425 Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners Anand Raghunathan, Ganesh Lakshminarayana, Kanishka Lahiri 2005-12-20
6324679 Register transfer level power optimization with emphasis on glitch analysis and reduction Anand Raghunathan 2001-11-27
6195786 Constrained register sharing technique for low power VLSI design Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha 2001-02-27
6105139 Controller-based power management for low-power sequential circuits Anand Raghunathan, Niraj K. Jha 2000-08-15
5748647 Low cost testing method for register transfer level circuits Subhrajit Bhattacharya 1998-05-05
5553000 Eliminating retiming bottlenecks to improve performance of synchronous sequential VLSI circuits Miodrag Potkonjak, Steven G. Rothweiler 1996-09-03
5550749 High level circuit design synthesis using transformations Miodrag Potkonjak 1996-08-27
5513123 Non-scan design-for-testability of RT-level data paths Miodrag Potkonjak 1996-04-30
5513118 High level synthesis for partial scan testing Miodrag Potkonjak, Rabindra K. Roy 1996-04-30
5502647 Resynthesis and retiming for optimum partial scan testing Srimat Chakradhar 1996-03-26
5448497 Exploiting multi-cycle false paths in the performance optimization of sequential circuits Pranav Ashar, Sharad Malik 1995-09-05