Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5875196 | Deriving signal constraints to accelerate sequential test generation | Srimat Chakradhar, Vijay Gangaram | 1999-02-23 |
| 5657240 | Testing and removal of redundancies in VLSI circuits with non-boolean primitives | Srimat Chakradhar, Vishwani D. Agrawal | 1997-08-12 |
| 5553000 | Eliminating retiming bottlenecks to improve performance of synchronous sequential VLSI circuits | Sujit Dey, Miodrag Potkonjak | 1996-09-03 |