Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12306247 | System and method for optimizing fault coverage based on optimized test point insertion determinations for logical circuits | Spencer K. Millican, Yang Sun, Soham Roy | 2025-05-20 |
| 6131181 | Method and system for identifying tested path delay faults | Michael L. Bushnell, Marwan A. Gharaybeh | 2000-10-10 |
| 5983007 | Low power circuits through hazard pulse suppression | — | 1999-11-09 |
| 5657240 | Testing and removal of redundancies in VLSI circuits with non-boolean primitives | Srimat Chakradhar, Steven G. Rothweiler | 1997-08-12 |
| 5606567 | Delay testing of high-performance digital components by a slow-speed tester | Tapan Jyoti Chakraborty | 1997-02-25 |
| 5590135 | Testing a sequential circuit | Miron Abramovici, Kwang-Ting Cheng, Krishna B. Rajan | 1996-12-31 |
| 5499249 | Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs) | Tapan Jyoti Chakraborty | 1996-03-12 |
| 5461573 | VLSI circuits designed for testability and methods for producing them | Srimat Chakradhar, Suman Kanjilal | 1995-10-24 |
| 5365528 | Method for testing delay faults in non-scan sequential circuits | Tapan Jyoti Chakraborty | 1994-11-15 |
| 5257268 | Cost-function directed search method for generating tests for sequential logic circuits | Prathima Agrawal, Kwang-Ting Cheng | 1993-10-26 |
| 5228040 | Testable implementations of finite state machines and methods for producing them | Kwang-Ting Cheng | 1993-07-13 |
| 5043986 | Method and integrated circuit adapted for partial scan testability | Kwang-Ting Cheng | 1991-08-27 |
| 4493077 | Scan testable integrated circuit | Melvin R. Mercer | 1985-01-08 |