Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8164345 | Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability | Raghuveer Ausoori, Omar B. Khan, Deepak Mehta, Xinghao Chen | 2012-04-24 |
| 7810053 | Method and system of dynamic power cutoff for active leakage reduction in circuits | Baozhen Yu | 2010-10-05 |
| 6812724 | Method and system for graphical evaluation of IDDQ measurements | Lan Rao | 2004-11-02 |
| 6308300 | Test generation for analog circuits using partitioning and inverted system simulation | Rajesh Ramadoss | 2001-10-23 |
| 6247154 | Method and apparatus for combined stuck-at fault and partial-scanned delay-fault built-in self test | Ganapathy Parthasarathy | 2001-06-12 |
| 6131181 | Method and system for identifying tested path delay faults | Marwan A. Gharaybeh, Vishwani D. Agrawal | 2000-10-10 |
| 5831437 | Test generation using signal flow graphs | Rajesh Ramadoss | 1998-11-03 |
| 5422891 | Robust delay fault built-in self-testing method and apparatus | Imtiaz P. Shaik | 1995-06-06 |