Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11041904 | Zero-pin test solution for integrated circuits | Umesh Srikantiah, Rachana Rout | 2021-06-22 |
| 10429441 | Efficient test architecture for multi-die chips | Alvin Leng Sun Loke, Hong Dai, Thomas Clark Bryan | 2019-10-01 |
| 10249380 | Embedded memory testing with storage borrowing | Roberto Fabian Averbuj | 2019-04-02 |
| 9285418 | Method and apparatus for characterizing thermal marginality in an integrated circuit | Rajamani Sethuram, Ratibor Radojcic | 2016-03-15 |
| 7962885 | Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing | Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Van Treuren | 2011-06-14 |
| 7958417 | Apparatus and method for isolating portions of a scan path of a system-on-chip | Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Van Treuren | 2011-06-07 |
| 7958479 | Method and apparatus for describing and testing a system-on-chip | Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Van Treuren | 2011-06-07 |
| 7954022 | Apparatus and method for controlling dynamic modification of a scan path | Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Van Treuren | 2011-05-31 |
| 7949915 | Method and apparatus for describing parallel access to a system-on-chip | Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Van Treuren | 2011-05-24 |
| 7689866 | Method and apparatus for injecting transient hardware faults for software testing | — | 2010-03-30 |
| 7594150 | Fault-tolerant architecture of flip-flops for transient pulses and signal delays | Aditya Jagirdar, Roystein Oliveira | 2009-09-22 |
| 7482831 | Soft error tolerant flip flops | Aditya Jagirdar, Roystein Oliveira | 2009-01-27 |
| 7284159 | Fault injection method and system | Chen-Huan Chiang | 2007-10-16 |
| 6378094 | Method and system for testing cluster circuits in a boundary scan environment | Bradford Van Treuren | 2002-04-23 |
| 6167542 | Arrangement for fault detection in circuit interconnections | Bradford Gene VanTreuren | 2000-12-26 |
| 6148425 | Bist architecture for detecting path-delay faults in a sequential circuit | Sudipta Bhawmik, Nilanjan Mukherjee | 2000-11-14 |
| 6124715 | Testing of live circuit boards | — | 2000-09-26 |
| 5606567 | Delay testing of high-performance digital components by a slow-speed tester | Vishwani D. Agrawal | 1997-02-25 |
| 5499249 | Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs) | Vishwani D. Agrawal | 1996-03-12 |
| 5365528 | Method for testing delay faults in non-scan sequential circuits | Vishwani D. Agrawal | 1994-11-15 |