Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12300337 | Memory repair system and method | Amir Borovietzky, Arvind Jain, Massine Bitam, Madan Krishnappa | 2025-05-13 |
| 11934219 | Integrated functional and design for testability (DFT) clock delivery architecture | Arvind Jain, Divya Gangadharan, Muhammad Anis Uddin Nasir, Madan Krishnappa | 2024-03-19 |
| 10429441 | Efficient test architecture for multi-die chips | Tapan Jyoti Chakraborty, Alvin Leng Sun Loke, Thomas Clark Bryan | 2019-10-01 |
| 6862705 | System and method for testing high pin count electronic devices using a test board with test channels | Richard T. Nesbitt, Jim Icuss | 2005-03-01 |
| 5691215 | Method for fabricating a sub-half micron MOSFET device with insulator filled shallow trenches planarized via use of negative photoresist and de-focus exposure | Chang-Ming Dai, Shih-Chang TAI | 1997-11-25 |