Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11444124 | Hybrid memristor/field-effect transistor memory cell and its information encoding scheme | Miguel Angel Lastras Montaño | 2022-09-13 |
| 7158970 | Maximizing expected generalization for learning complex query concepts | Edward Chang | 2007-01-02 |
| 6976016 | Maximizing expected generalization for learning complex query concepts | Edward Chang | 2005-12-13 |
| 6694466 | Method and system for improving the test quality for scan-based BIST using a general test application scheme | Huan-Chih Tsai, Sudipta Bhawmik | 2004-02-17 |
| 6463561 | Almost full-scan BIST method and system having higher fault coverage and shorter test application time | Sudipta Bhawmik, Huan-Chih Tsai | 2002-10-08 |
| 6345373 | System and method for testing high speed VLSI devices using slower testers | Srimat Chakradhar, Angela Krstic | 2002-02-05 |
| 6256759 | Hybrid algorithm for test point selection for scan-based BIST | Sudipta Bhawmik, Chih-Jen Lin, Huan-Chih Tsai | 2001-07-03 |
| 6018813 | Identification and test generation for primitive faults | Srimat Chakradhar, Angela Krstic | 2000-01-25 |
| 5828828 | Method for inserting test points for full-and-partial-scan built-in self-testing | Chih-Jen Lin | 1998-10-27 |
| 5710711 | Method and integrated circuit adapted for partial scan testability | Jing-Yang Jou | 1998-01-20 |
| 5590135 | Testing a sequential circuit | Miron Abramovici, Vishwani D. Agrawal, Krishna B. Rajan | 1996-12-31 |
| 5587919 | Apparatus and method for logic optimization by redundancy addition and removal | Luis Entrena | 1996-12-24 |
| 5513122 | Method and apparatus for determining the reachable states in a hybrid model state machine | Anjur Sundaresan Krishnakumar | 1996-04-30 |
| 5257268 | Cost-function directed search method for generating tests for sequential logic circuits | Prathima Agrawal, Vishwani D. Agrawal | 1993-10-26 |
| 5228040 | Testable implementations of finite state machines and methods for producing them | Vishwani D. Agrawal | 1993-07-13 |
| 5043986 | Method and integrated circuit adapted for partial scan testability | Vishwani D. Agrawal | 1991-08-27 |