Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393842 | System and method for incremental learning using a grow-and-prune paradigm with neural networks | Xiaoliang Dai, Hongxu Yin | 2025-08-19 |
| 12383206 | System and method for testing for SARS-COV-2/COVID-19 based on wearable medical sensors and neural networks | Shayan HASSANTABAR | 2025-08-12 |
| 11973771 | System and method for security in Internet-of-Things and cyber-physical systems based on machine learning | Tanujay Saha, Najwa Aaraj | 2024-04-30 |
| 11783060 | System and method for energy efficient sensors with compression, artificial intelligence, and security | — | 2023-10-10 |
| 11521068 | Method and system for neural network synthesis | Xiaoliang Dai, Hongxu Yin | 2022-12-06 |
| 10986994 | Stress detection and alleviation system and method | Ayten Ozge Akmandor | 2021-04-27 |
| 10798238 | System and method for tracking a mobile device user | Arsalan Mosenia, Xiaoliang Dai, Prateek Mittal | 2020-10-06 |
| 10722719 | Vibration-based secure side channel for medical devices | Younghyun Kim, Woo Suk Lee, Vijay Raghunathan, Anand Raghunathan | 2020-07-28 |
| 10652237 | Continuous authentication system and method based on BioAura | Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan | 2020-05-12 |
| 10506433 | Secure optical communication channel for implantable medical devices | Arsalan Mosenia | 2019-12-10 |
| 10135849 | Securing medical devices through wireless monitoring and anomaly detection | Anand Raghunathan, Meng Zhang | 2018-11-20 |
| 9735783 | Fine-grain dynamically reconfigurable FPGA architecture | Ting-Jung Lin, Wei Zhang | 2017-08-15 |
| 9099195 | Hybrid nanotube/CMOS dynamically reconfigurable architecture and system therefore | Wei Zhang, Li Shang | 2015-08-04 |
| 8990740 | Method and system for a run-time reconfigurable computer architecture | Wei Zhang, Li Shang | 2015-03-24 |
| 8117436 | Hybrid nanotube/CMOS dynamically reconfigurable architecture and an integrated design optimization method and system therefor | Wei Zhang, Li Shang | 2012-02-14 |
| 7278123 | System-level test architecture for delivery of compressed tests | Srivaths Ravi, Anand Raghunathan, Loganathan Lingappan, Srimat Chakradhar | 2007-10-02 |
| 7260809 | Power estimation employing cycle-accurate functional descriptions | Srivaths Ravi, Anand Raghunathan, Lin Zhong | 2007-08-21 |
| 6463560 | Method for implementing a bist scheme into integrated circuits for testing RTL controller-data paths in the integrated circuits | Sudipta Bhawmik, Indradeep Ghosh | 2002-10-08 |
| 6308313 | Method for synthesis of common-case optimized circuits to improve performance and power dissipation | Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri | 2001-10-23 |
| 6289488 | Hardware-software co-synthesis of hierarchical heterogeneous distributed embedded systems | Bharat Dave | 2001-09-11 |
| 6195786 | Constrained register sharing technique for low power VLSI design | Anand Raghunathan, Sujit Dey, Ganesh Lakshminarayana | 2001-02-27 |
| 6117180 | Hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance | Bharat Dave | 2000-09-12 |
| 6110220 | Concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures | Bharat Dave | 2000-08-29 |
| 6112023 | Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems | Bharat Dave, Ganesh Lakshminarayana | 2000-08-29 |
| 6105139 | Controller-based power management for low-power sequential circuits | Sujit Dey, Anand Raghunathan | 2000-08-15 |