Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7987412 | Reed Solomon decoding of signals having variable input data rates | Jayanta Das | 2011-07-26 |
| 7319555 | Integrated performance monitoring, performance maintenance, and failure detection for photonic regenerators | Ruomei Mu, Hongsheng Wang, Jithamithra Sarathy, Boris Stefanov | 2008-01-15 |
| 7239768 | Photonic integrated circuit | Jithamithra Sarathy, Boris Stefanov | 2007-07-03 |
| 7190909 | Generation and detection of optical maintenance signals in optical networks | Jayanta Das, Kuo-Ming Lee, Roman Antosik, Scott Kaminski, Jithamithra Sarathy +3 more | 2007-03-13 |
| 6978425 | Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners | Anand Raghunathan, Kanishka Lahiri, Sujit Dey | 2005-12-20 |
| 6735744 | Power mode based macro-models for power estimation of electronic circuits | Anand Raghunathan, Nachiketh Rao Potlapally, Michael Hsiao, Srimat Chakradhar | 2004-05-11 |
| 6694488 | System for the design of high-performance communication architecture for system-on-chips using communication architecture tuners | Anand Raghunathan, Kanishka Lahiri | 2004-02-17 |
| 6625781 | Multi-level power macromodeling | Wolfgang Roethig, Anand Raghunathan, Arun Balakrishnan | 2003-09-23 |
| 6308313 | Method for synthesis of common-case optimized circuits to improve performance and power dissipation | Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha | 2001-10-23 |
| 6275969 | Common case optimized circuit structure for high-performance and low-power VLSI designs | Anand Raghunathan | 2001-08-14 |
| 6195786 | Constrained register sharing technique for low power VLSI design | Anand Raghunathan, Sujit Dey, Niraj K. Jha | 2001-02-27 |
| 6112023 | Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems | Bharat Dave, Niraj K. Jha | 2000-08-29 |