Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10599800 | Formal clock network analysis, visualization, verification and generation | Hans-Joerg Peter, Guillaume Plassan, Barsneya Chakrabarti, Mohammad H. Movahed-Ezazi | 2020-03-24 |
| 10387605 | System and method for managing and composing verification engines | Maher Mneimneh, Scott Cotton, Fahim Rahim, Sudeep Mondal, Paras Mal Jain | 2019-08-20 |
| 10289773 | Reset domain crossing management using unified power format | Deep Shah, Namit Gupta | 2019-05-14 |
| 9721058 | System and method for reactive initialization based formal verification of electronic logic design | Hans-Jorg Peter, Barsneya Chakrabarti, Fahim Rahim, Mohammad H. Movahed-Ezazi | 2017-08-01 |
| 9721057 | System and method for netlist clock domain crossing verification | Malay Ganai, Maher Mneimneh, Paras Mal Jain, Mohammad H. Movahed-Ezazi, Pronay Kumar Biswas +1 more | 2017-08-01 |
| 9208272 | Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design | — | 2015-12-08 |
| 8984457 | System and method for a hybrid clock domain crossing verification | Maher Mneimneh, Mohammad H. Movahed-Ezazi | 2015-03-17 |
| 8656328 | System and method for abstraction of a circuit portion of an integrated circuit | Mohammed Movahed-Ezazi, Barsneya Chakrabarti, Manish Gupta, Chandan Kumar | 2014-02-18 |
| 8607173 | Hierarchical bottom-up clock domain crossing verification | Maher Mneimneh, Paras Mal Jain, Deepak P. Ahuja, Mohammad H. Movahed-Ezazi | 2013-12-10 |
| 8560988 | Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design | — | 2013-10-15 |
| 7506292 | Method for clock synchronization validation in integrated circuit design | Mohammad Movahed Ezazi, Bernard Murphy | 2009-03-17 |
| 7073146 | Method for clock synchronization validation in integrated circuit design | Mohammad Movahed Ezazi, Bernard Murphy | 2006-07-04 |